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The rapid development of quantum computing constitutes a significant threat to modern Public-Key Cryptography (PKC). key, signature and Key Encapsulation Mechanism (KEM) sysThe use of Shor's algorithm [1] with potential powerful tem based on a double exponentiation with matrix exponents. quantum computers could easily break the two most widely In this paper, a high-throughput pipelined architecture of used public key cryptosystems, namely, RSA and Elliptic DME-(3,2,48), with $m =3 , n =2$, and $q = 2 ^{e}\,= 2 ^{48}$, has been Curve Cryptography (ECC), based on integer factorization and presented and hardware implementations over Xilinx FPGAs discrete logarithm problems. For this reason, Post-Quantum Artix-7 have been performed. These settings correspond with Cryptography (PQC) [2] based on alternative mathematical the reference implementation given in the NIST proposal [7], features has become a fundamental research topic due to its where the finite field $GF( 2 ^{48})$ is generated by the type I resistance against quantum computers. The National Institute of Standards and Technology (NIST) has even opened a call for proposals of quantum-resistant PKC algorithms in order to standardize one or more PQC algorithms. Cryptographic systems that appear to be extremely difficult to break with large quantum computers are hash-based cryptography, lattice-based cryptography, code-based cryptography, and multivariate-quadratic cryptography [3]. Furthermore, efficient hardware implementations are highly required for these alternative quantum-resistant cryptosystems [4].

This paper details the design of a new high-speed point multiplier for elliptic curve cryptography using either field-programmable gate array or application-specified integrated circuit technology. Different levels of digit-serial computation were applied to the data path of Galois field (GF) multiplication and division to explore the resulting performances and find out an optimal digit size. We provide results for the five National Institute of Standards and Technology recommended curves, outperforming the previous published results. In GF(2163), we achieve a point multiplication in 19.38 μs in Xilinx Virtex-E. Using the modern Xilinx Virtex-5, the point multiplication times in GF(2m) for m = 163, 233, 409, and 571 are 5.5, 17.8, 33.6, 102.6, 384μs, respectively, which are the fastest figures reported to date.

Modular exponentiation with large modulus and exponent, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems. Typically, the Montgomery's modular-multiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. In this paper, we optimize the Montgomery's multiplication and propose architectures to perform the least significant bit first and the most significant bit first algorithms. The developed architecture has the following distinctive characteristics: 1) use of digit serial approach for Montgomery multiplication. 2) Conversion of the CSA representation of intermediate multiplication using carry-skip addition. This allows the critical path to be reduced, albeit with a small-area speed penalty; and 3) precompute the quotient value in Montgomery's iteration in order to speed up the operating frequency. In this paper, we present results in Xilinx Virtex 5 and in 0.18-μm application-specified integrated circuit technologies. For fair comparison with previous works, Xilinx Virtex 2 results are reported. Experimental results show that the proposed modular exponentiation and modular-multiplication design obtain the best delay performance compared with the published works and outperform them in terms of area-time complexity as well.

A new formulation for the canonical basis multiplication in the finite fields GF(2/sup m/) based on the use of a triangular basis and on the decomposition of a product matrix is presented. From this algorithm, a new method for multiplication (named transpositional) applicable to general irreducible polynomials is deduced. The transpositional method is based on the computation of 1-cycles and 2-cycles given by a permutation defined by the coordinate of the product to be computed and by the cardinality of the field GF(2/sup m/). The obtained cycles define groups corresponding to subexpressions that can be shared among the different product coordinates. This new multiplication method is applied to five types of irreducible trinomials. These polynomials have been widely studied due to their low-complexity implementations. The theoretical complexity analysis of the corresponding bit-parallel multipliers shows that the space complexities of our multipliers match the best results known to date for similar canonical GF(2/sup m/) multipliers. The most important new result is the reduction, in two of the five studied trinomials, of the time complexity with respect to the best known results.

Galois (or finite) fields are used in a wide number of technical applications, playing an important role in several areas such as cryptographic schemes and algebraic codes, used in modern digital communication systems. Finite field arithmetic must be fast, due to the increasing performance needed by communication systems, so it might be necessary for the implementation of the modules performing arithmetic over Galois fields on semiconductor integrated circuits. Galois field multiplication is the most costly arithmetic operation and different approaches can be used. In this paper, the fundamentals of Galois fields are reviewed and multiplication of finite-field elements using three different representation bases are considered. These three multipliers have been implemented using a bit-parallel architecture over reconfigurable hardware and experimental results are presented to compare the performance of these multipliers.