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This paper presents IOb-SoC, a template for modular System-on-Chip (SoC) for teaching, research and innovation. IOb-SoC can be customized to implement highly specialized SoCs with varying degrees of complexity. Its hardware is described in (System-)Verilog and its applications are programmed in C/C++. IOb-SoC is hosted at GitHub, and the repository includes automation scripts to enable simulation, synthesis and place and route of both Field-Programmable Gate Array (FPGA) and Integrated Circuit (IC), using both free and commercial tools. At the centre of IOb-SoC lies a RISC-V processor, the PicoRV32. This RISC-V processor is the default, but IOb-SoC can use other processors. IOb-SoC is released in the public domain under the MIT permissive license. By providing the code publicly and at no charge, IOb-SoC can be used by teachers, researchers, and industrial innovators. The advantage of IOb-SoC is that of being straightforward to set up and quick to grasp. It is also modular to be personalized for applications in different contexts. IOb-SoC is supported in a few FPGA boards from different vendors, and also in an IC UMC 130nm technology node; it can easily port to new boards or IC technologies.

Convolutional neural networks have become the state of the art of machine learning for a vast set of applications, especially for image classification and object detection. There are several advantages to running inference on these models at the edge, including real-time performance and data privacy. The high computing and memory requirements of convolutional neural networks have been major obstacles to the broader deployment of CNNs on edge devices. Data quantization is an optimization method that reduces the number of bits used to represent weights and activations of a network model, minimizing storage requirements and computing complexity. Quantization can be applied at the layer level, by using different bit widths in different layers: this is called hybrid quantization. This article proposes a new efficient and configurable architecture for running CNNs with hybrid quantization in low-density Field-Programmable Gate Arrays (FPGAs) targeting edge devices. The architecture has been implemented on the Xilinx ZYNQ7020/45 devices and is running the AlexNet and VGG16 networks. Running AlexNet, the architecture has a throughput up to 508 images per second on the ZYNQ7020 device, and 1639 images per second on the ZYNQ7045 device. Considering VGG16, the architecture delivers up to 43 images per second on the ZYNQ7020 device, and 81 images per second on the ZYNQ7045 device. The proposed hybrid architecture achieves up to $13.7\times $ improvement in performance compared to state-of-the-art solutions, with small accuracy degradation.

Object detection and classification is an essential task of computer vision. A very efficient algorithm for detection and classification is YOLO (You Look Only Once). We consider hardware architectures to run YOLO in real-time on embedded platforms. Designing a new dedicated accelerator for each new version of YOLO is not feasible given the fast delivery of new versions. This work’s primary goal is to design a configurable and scalable core for creating specific object detection and classification systems based on YOLO, targeting embedded platforms. The core accelerates the execution of all the algorithm steps, including pre-processing, model inference and post-processing. It considers a fixed-point format, linearised activation functions, batch-normalisation, folding, and a hardware structure that exploits most of the available parallelism in CNN processing. The proposed core is configured for real-time execution of YOLOv3-Tiny and YOLOv4-Tiny, integrated into a RISC-V-based system-on-chip architecture and prototyped in an UltraScale XCKU040 FPGA (Field Programmable Gate Array). The solution achieves a performance of 32 and 31 frames per second for YOLOv3-Tiny and YOLOv4-Tiny, respectively, with a 16-bit fixed-point format. Compared to previous proposals, it improves the frame rate at a higher performance efficiency. The performance, area efficiency and configurability of the proposed core enable the fast development of real-time YOLO-based object detectors on embedded systems.

Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

Deep learning is now present in a wide range of services and applications, replacing and complementing other machine learning algorithms. Performing training and inference of deep neural networks using the cloud computing model is not viable for applications where low latency is required. Furthermore, the rapid proliferation of the Internet of Things will generate a large volume of data to be processed, which will soon overload the capacity of cloud servers. One solution is to process the data at the edge devices themselves, in order to alleviate cloud server workloads and improve latency. However, edge devices are less powerful than cloud servers, and many are subject to energy constraints. Hence, new resource and energy-oriented deep learning models are required, as well as new computing platforms. This paper reviews the main research directions for edge computing deep learning algorithms.

This paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the $C/I_{1~\textrm {MHz}}$ , and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node ( $0.13~\mu \text{m}$ ), occupying a silicon area smaller than 0.7 mm2. The receiver achieves a sensitivity level of −92 dBm while consuming 1.41 mA from a 1.2-V supply.

Object detection is an important task for many applications, like transportation, security, and medical applications. Many of these applications are needed on edge devices to make local decisions. Therefore, it is necessary to provide low-cost, fast solutions for object detection. This work proposes a configurable hardware core on a field-programmable gate array (FPGA) for object detection. The configurability of the core allows its deployment on target devices with diverse hardware resources. The object detection accelerator is based on YOLO, for its good accuracy at moderate computational complexity. The solution was applied to the design of a core to accelerate the Tiny-YOLOv3, based on a CNN developed for constrained environments. However, it can be applied to other YOLO versions. The core was integrated into a full system-on-chip solution and tested with the COCO dataset. It achieved a performance from 7 to 14 FPS in a low-cost ZYNQ7020 FPGA, depending on the quantization, with an accuracy reduction from 2.1 to 1.4 points of mAP50.

Background: Pleural effusions constitute one of the most frequent pathologies encountered in the pulmonary service of Maputo Central Hospital (MCH) in Mozambique. Bleomycin and talc are commonly used for pleurodesis, but cost prohibitive, therefore we aimed to retrospectively compare the efficacy and safety of sodium hydroxide (NaOH) with bleomycin for pleurodesis. Methods: Case records of pleurodesis using bleomycin and NaOH from 2002 to 2013 were reviewed. Standard of care for pleurodesis for recurrent pleural effusions at MCH was developed using the materials available. NaOH remained the agent of choice until 2006 when bleomycin became available. Clinical data regarding general complications, rate of success and lung expansion were noted for every patient who underwent pleurodesis at MCH during this time frame. Results: Review of pleurodesis at MCH revealed 24 cases using bleomycin and 23 cases using NaOH as the sclerosing agent. Patient characteristics were balanced between the two groups with majority of pleural effusions malignant in etiology. Conclusions: There was no statistically significant difference between the use of bleomycin and NaOH as defined by lung expansion. General complications were observed less frequently in 2 (10%) of patients treated with NaOH compared with 8 (38%) of patients using bleomycin. Only three patients presented with recurrent pleural effusion after pleurodesis with NaOH. NaOH may offer a low cost alternative sclerosing agent for resource limited areas.

This paper presents an implementation of a Convolutional Neural Network (CNN) algorithm using a linear array of full mesh dynamically and partially reconfigurable Coarse Grained Reconfigurable Arrays (CGRAs). Accelerating CNNs using GPUs and FPGAs is more common and there are few works that address the topic of CNN acceleration using CGRAs. Using CGRAs can bring size and power advantages compared to GPUs and FPGAs. The contribution of this paper is to study the performance of full mesh dynamically and partially reconfigurable CGRAs for CNN acceleration. The CGRA used is an improved version of the previously published Versat CGRA, adding multi CGRA core support and pre-silicon configurability. The results show that the proposed CGRA is as easy to program as the original full mesh Versat CGRA, and that its performance and power consumption scale linearly with the number of instances.

Convolutional Neural Networks (CNN) are quite useful in edge devices for security, surveillance, and many others. Running CNNs in embedded devices is a design challenge since these models require high computing power and large memory storage. Data quantization is an optimization technique applied to CNN to reduce the computing and memory requirements. The method reduces the number of bits used to represent weights and activations, which consequently reduces the size of operands and of the memory. The method is more effective if hybrid quantization is considered in which data in different layers may have different bit widths. This article proposes a new hardware module to calculate dot-products of CNNs with hybrid quantization. The module improves the implementation of CNNs in low density FPGAs, where the same module runs dot-products of different layers with different data quantizations. We show implementation results in ZYNQ7020 and compare with state-of-the-art works. Improvements in area and performance are achieved with the new proposed module.

The idea of combining multiple CPU and CGRA cores is not in itself original but detailed characterizations of such architectures and measurements on compelling applications are difficult to find in the literature. Although commercial CPUs, GPUs and FPGAs are widely available, there are no commercial CGRAs, which may be attributed to the lack of metrics on performance, energy and cost. In this paper, we introduce a heterogeneous computing platform consisting of several RISC-V CPU and Versat CGRA cores. Implementation results for several instances of the architecture are presented. The CPU of choice is the promising open source RISC-V architecture, which has never been featured in CPU/CGRA architectures. This paper presents independent implementations of two RISC-V cores: a minimal one, useful as a simple controller, and a more performant 5-stage pipeline implementation. The RISC-V cores have been designed using the recent Chisel HDL, useful for automating tasks pertaining to the writing of RTL. The selected CGRA is the published Versat architecture, for which 4 different instances have been created. Implementation results for 2 FPGA families and ASIC technology nodes are presented: area, frequency and power. Applications cover digital audio and machine learning, demonstrating the versatility of the proposed platform at competitive area, frequency and energy footprints.

Due to the computational complexity of Convolutional Neural Networks (CNNs), high performance platforms are generally considered for their execution. However, CNNs are very useful in embedded systems and its execution right next to the source of data has many advantages, like avoiding the need for data communication. In this paper, we propose an architecture for CNN inference (Lite-CNN) that can achieve high performance in low density FPGAs. Lite-CNN adopts a fixed-point representation for both neurons and weights, which was already shown to be sufficient for most CNNs. Also, with a simple and known dot product reorganization, the number of multiplications is reduced to half. We show implementation results for 8 bit fixed-point in a ZYNQ7020 and extrapolate for other larger FPGAs. Lite-CNN achieves 410 GOPs in a ZYNQ7020.

Deep neural networks have recently shown great results in a vast set of image applications. The associated deep learning models are computationally very demanding and, therefore, several hardware solutions have been proposed to accelerate their computation. FPGAs have recently shown very good performances for these kind of applications and so it is considered a promising platform to accelerate the execution of deep learning algorithms. A common operation in these algorithms is multiply-accumulate (MACC) that is used to calculate dot-products. Since many dot products can be calculated in parallel, as long as memory bandwidth is available, it is very important to implement this operation very efficiently to increase the density of MACC units in an FPGA. In this paper, we propose an implementation of parallel MACC units in FPGA for dot-product operations with very high performance/area ratios using a mix of DSP blocks and LUTs. We consider fixed-point representations with 8 bits of size, but the method can be applied to other bit widths. The method allows us to achieve TOPs performances, even for low cost FPGAs.

In this paper we present a k-means clustering algorithm for the Versat architecture, a small and low power Coarse Grained Reconfigurable Array (CGRA). This algorithm targets ultra low energy devices where using a GPU or FPGA accelerator is out of the question. The Versat architecture has been enhanced with pointer support, the possibility of using the address generators for general purposes, and cumulative and conditional operations for the ALUs. The algorithm is based on two hardware datapaths for the two basic steps of the algorithm: the assignment and the update steps. The program is fully parameterizable with the number of datapoints, centroids, coordinates, and memory pointers for reading and writing the data. The execution time scales linearly with the number of datapoints, centers or dimensions. The results show that the new Versat core is 9.4× smaller than an ARM Cortex A9 core, runs the algorithm 3.8× faster and consumes 46.3× less energy.

This paper describes the use of scale estimators in field trials for mapping ground targets by an aerial vehicle with onboard sensing. Targets are assumed to be static and of a known shape. The vehicle is a lightweight, tethered, airship with onboard global positioning system, magnetometer, 3-axis accelerometer and gyro sensors, and a camera. The dynamics, trajectory, and sensing noise characteristics, are assumed a priori unknown. The paper focus on the use of scale estimators to minimize the influence of the outlier measurements in the mean and covariance of the target positions observed as the vehicle moves. The results obtained show an interesting performance, better than that obtained with common maximum likelihood mean and covariance estimators, namely a smaller uncertainty is achieved.

This paper introduces Versat, a minimal Coarse-Grain Reconfigurable Array (CGRA) used as a hardware accelerator to optimize performance and power in a heterogeneous system. Compared to other works, Versat features a smaller number of functional units and a simpler controller, mainly used for reconfiguration and data transfer control. This stems from the observation that competitive acceleration can be achieved with a smaller array and more flexible reconfigurations. Partial reconfiguration plays a central role in Versat’s runtime reconfiguration scheme. Results on core area, frequency, power and performance are presented and compared to other implementations.

This paper presents a digital low-IF Gaussian frequency-shift keying (GFSK) demodulator. The demodulator is based on a phase-shift quadrature discriminator. A preamble detector controls the sequencing of the blocks operation to minimize power consumption. An IF input signal of 1 MHz is used, the same of the data rate, hence, allowing a low-power receiver implementation. The implementation is fully digital with a silicon area of 0.06 mm2 in 130 nm process. Simulations show a state-of-art current consumption of about 143 μA from a single 1.2 V supply voltage. The proposed demodulator requires a SNR of 15 dB for a BER of 0.1 % for up to ± 200 kHz frequency offset variation.

In recent years backtrack search algorithms for propositional satisfiability (SAT) have been the subject of dramatic improvements. These improvements allowed SAT solvers to successfully solve instances with thousands or tens of thousands of variables. However, many new challenging problem instances are still too hard for current SAT solvers. As a result, further improvements to SAT technology are expected to have key consequences in solving hard real-world instances. This paper introduces a new idea: choosing the backtrack variable using a heuristic approach with the goal of diversifying the regions of the space that are explored during the search. The proposed heuristics are inspired by the heuristics proposed in recent years for the decision branching step of SAT solvers, namely, VSIDS and its improvements. Completeness conditions are established, which guarantee completeness for the new algorithm, as well as for any other incomplete backtracking algorithm. Experimental results on hundreds of instances derived from real-world problems show that the new technique is able to speed SAT solvers, while aborting fewer instances. These results clearly motivate the integration of heuristic backtracking in SAT solvers.

In this paper, we present the architecture of a new SAT solver using reconfigurable logic and a virtual logic scheme. Our main contributions include new forms of massive fine-grain parallelism, structured design techniques based on iterative logic arrays that reduce compilation times from hours to minutes, and a decomposition technique that creates independent subproblems that may be concurrently solved by unconnected FPGAs. The decomposition technique is the basis of the virtual logic scheme, since it allows solving problems that exceed the hardware capacity. Our architecture is easily scalable. Our results show several orders of magnitude speedup compared with a state-of-the-art software implementation, and also with respect to prior SAT solvers using reconfigurable hardware.

Test quality requires the ability of test patterns to cover realistic faults originated by physical defects induced during IC manufacturing. Recent progress in a methodology for physical testability analysis is reported in this paper. A refined bridging faults classification provides evidence that reconvergent fan-out areas should be carefully designed to avoid hard to detect faults. Moreover, the concept of selective decompaction is introduced, to show that with reduced area overhead, testability can significantly be increased. As a result, guidelines for cell library development, and for refined routing algorithms, are presented. The results are il1ustra.ted with several design examples. These examples also show that the realistic fault coverage can be higher or lower than the Line Stuck-At (LSA) fault coverage depending on the relative incidence of bridging and open faults, and the topological characteristics of the surrounding circuit.

This paper presents a new model for evaluating the defect level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T) from the one estimated by the Williams-Brown equation is shown, to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T) experimental results on actual ICs. >

This paper presents DARP, a novel digital audio signal re-configurable processor based on the low cost Spartan II XC2S200 FPGA device. The system can handle several tens of digital audio signals in parallel, and can be programmed and controlled by a host computer. Its main advantages are: multi-functionality, high performance, low cost and low power. Several digital audio cores have been developed, which can be combined in different ways to implement a variety of complex digital audio algorithms in DARP. Several expensive commercial systems would be needed to achieve the processing power that is possible with DARP. A case study of an 8x8 stereo audio matrix and format converter is presented. Our area, frequency and latency results show that FPGAs can compete with ASIC, processor or DSP solutions for implementing complex, cost effective and flexible digital audio systems.

We have found that the progress of developer base into films of terpolymers of norbornene (NB)-maleic anhydride (MA) and acrylic acid (AA) is a percolation process with a critical site concentration of x(c) equals 0.084 which suggests that every acrylic acid site in the terpolymer of norbornene-maleic anhydride-acrylic acid can make 12 monomer units of the polymer water compatible. In practice these systems are being used with various tert-butyl esters of cholic acid as dissolution inhibitors. The cholates differ very much in their dissolution inhibition factors (lowest t-butyl cholate (1.3) to highest t-butyl lithocholate glutarate dimer (7.4). The change in these factors corrected for molarity follow the hydrophobic character of the dissolution as measured by log(p). A quick screening method has also been established to evaluate dissolution inhibitors based on our observation that the cloud point (the volume % acetone in a water/acetone which gives persistent cloudiness) parallels the dissolution inhibiting power as measured by the dissolution inhibition factor. For dissolution promotion, optimal results are obtained with t-butyl 1,3,5-cyclohexanetricarboxylate (f equals -6.3) and poorest results with t-butyl lithocholate (f equals -2.8); this appears to track with the number of carboxyl groups and the hydrophobicity of the carboxylic acids. The Rmax found for resist formulations tracks well with these findings. Another factor in determining the ultimate achievable contrast is the degree of acidolytic deprotection achieved by the material. It appears that acidolyticaly cleaveable carboxylate esters with a higher concentration of electron withdrawing groups such as t-butyl 1,3,5-cyclohexanetricarboxylate are more effective.

This paper presents a review of existing defect level models and introduces a new defect level model that accounts for the fault clustering effect. The model uses generalized negative binomial statistics to model the probability distribution of the number of faults in a chip. This analysis shows that clustering, in addition to naturally increasing the yield, also raises the detection probability and therefore lowers the defect level. By accounting for clustering, the new model predicts a less stringent fault coverage requirement than other models.