252 results on '"Joseph S. Chang"'
Search Results
2. A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters.
3. An Accurate Digital Inductor Current Sensor for Current-Ripple-Based DC-DC Converters.
4. An Integrated DC-DC Converter with Novel Asymmetrical Segmented Power-Stages for Sustained High Power-Efficiencies.
5. A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors.
6. An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
7. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
8. Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
9. A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
10. A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency.
11. Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design.
12. Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
13. A Monolithic I2V2-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting.
14. A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation.
15. Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters.
16. Flexible Hybrid Electronics: Review and Challenges.
17. An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters.
18. Single-Event-Transient Resilient Memory for DSP in Space Applications.
19. A Circuit for Reducing the Reverse Current in DCM DC-DC Converters.
20. A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs.
21. A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications.
22. Flexible Electronic Skin: From Humanoids to Humans.
23. A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters.
24. A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation.
25. Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK.
26. A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters.
27. A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS.
28. A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters.
29. A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range.
30. Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
31. A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme.
32. A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network.
33. A review of audio Class D amplifiers.
34. Substrate thickness effect on transformer.
35. Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
36. An investigation of THD of a BTL Class D amplifier.
37. Fully-additive printed electronics: Process Development Kit.
38. A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands.
39. Printed Electronics: Effects of Bending and a Self-Compensation Means.
40. A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches.
41. Guest Editorial Organic/Printed Electronics: A Circuits and Systems Perspective.
42. A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point.
43. A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS.
44. Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
45. A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier.
46. Design of a variable-delay window ADC for switched-mode DC-DC converters.
47. A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline.
48. High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
49. A self-oscillating class D audio amplifier with dual voltage and current feedback.
50. A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.