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The new LHCb Vertex Locator (VELO) for LHCb, comprising a new pixel detector and readout electronics, will be installed in 2021 for data taking in Run 3 at the LHC. The electronics centers around the "VeloPix" ASIC at the front-end operating in a trigger-less readout at 40MHz. A custom serializer, called gigabit wireline transmitter (GWT), and associated custom protocol have been designed for the VeloPix. The GWT data are sent from the serializers of the VeloPix at a line rate of 5.12 Gb/s, reaching a total data rate of 2-3 Tb/s for the full VELO detector. Data are sent over 300-m optic-fiber links to the control and readout electronics cards for deserialization and processing in Intel Arria 10 FPGAs. Because of the VeloPix trigger-less design, latency variances up to 12 mu s can occur between adjacent datagrams. It is therefore essential to buffer and synchronize the data in firmware prior to onward propagation or suffer a huge CPU-processing penalty. This article will describe the architecture of the readout firmware in detail with focus given to the resynchronization mechanism and techniques for cauterization. Issues found during readout commissioning, and scaling resource utilization, along with the their solutions, will be illustrated. The latest results of the firmware data-processing chain can be presented as well as the verification procedures employed in simulation. Challenges for the next generation of the detector will also be presented with ideas for a readout processing solution. The new LHCb Vertex Locator (VELO) for LHCb, comprising a new pixel detector and readout electronics, will be installed in 2021 for data taking in Run 3 at the LHC. The electronics centers around the 'VeloPix' ASIC at the front-end operating in a trigger-less readout at 40MHz. A custom serializer, called gigabit wireline transmitter (GWT), and associated custom protocol have been designed for the VeloPix. The GWT data are sent from the serializers of the VeloPix at a line rate of 5.12 Gb/s, reaching a total data rate of 2-3 Tb/s for the full VELO detector. Data are sent over 300-m optic-fiber links to the control and readout electronics cards for deserialization and processing in Intel Arria 10 FPGAs. Because of the VeloPix trigger-less design, latency variances up to 12 $\mu \text{s}$ can occur between adjacent datagrams. It is therefore essential to buffer and synchronize the data in firmware prior to onward propagation or suffer a huge CPU-processing penalty. This article will describe the architecture of the readout firmware in detail with focus given to the resynchronization mechanism and techniques for cauterization. Issues found during readout commissioning, and scaling resource utilization, along with the their solutions, will be illustrated. The latest results of the firmware data-processing chain can be presented as well as the verification procedures employed in simulation. Challenges for the next generation of the detector will also be presented with ideas for a readout processing solution.

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of ~40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at ~5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above ~900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.

SUMMARY This paper presents a compatibility analysis involving space research service lunar mission uplink transmissions and the inter-satellite links of non-geostationary orbit systems operating in the 22-GHz band. Three points differentiate this analysis from the currently available studies: (1) the mathematical model used here allows for the consideration of the time varying nature of the inclination of the Moon orbital plane; (2) besides the usual unconditional interference cumulative distribution functions, this analysis also considers the conditional cumulative distribution functions given that the victim satellite is receiving interference, important to characterize the interference affecting users that, because of their location, are most of the time using satellites, which are under interference; and (3) instead of dynamic time simulation, the analytical method in Recommendation ITU-R S.1529 is used to determine the various cumulative distribution functions involved. Four scenarios are examined in the paper. Their main differences concern the number and location of the space research service transmitting Earth stations and the strategy under which they are active (transmitting). In all scenarios, cumulative distribution functions of the ratio I/N were determined for both the in-band and the out-of-band interference cases. Copyright © 2012 John Wiley & Sons, Ltd.