28 results on '"Juge, Andre"'
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2. Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature
3. Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs
4. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
5. Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K
6. Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET
7. RF performances at cryogenic temperatures of inductances integrated in a FDSOI technology
8. Modeling of MOSFET parasitic capacitances, and their impact on circuit performance
9. L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology
10. Electrostatics and channel coupling on 28 nm FD-SOIfor cryogenic applications
11. Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications
12. Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET
13. Characterization Methodology and Physical Compact Modeling of in-Wafer Global and Local Variability
14. New physical insight for analog application in PSP bulk compact model
15. Analog RF and mm-Wave design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA
16. Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET
17. Sensitivity analysis of C-V global variability for 28 nm FD-SOI
18. Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI
19. Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model
20. Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description
21. Experimental gm/{I}{D} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET.
22. Test structures for interdie variations monitoring in presence of statistical random variability
23. Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations
24. Monitoring variability of channel doping profile in the 45nm node MOSFET through reverse engineering of electrical back-bias effect
25. Chip-package interactions: Some investigations on copper/Low-k interconnect delaminations
26. Extrinsic, Parasitic Capacitance Contributions of MOSFETs, their Impact on Performance, and their Modeling
27. 4906921 Structure and process for testing integrated circuits permitting determination of the properties of layers
28. Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET
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