25 results on '"Jun Ho Bahn"'
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2. Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip.
3. Self-optimized Routing in a Network on-a-Chip.
4. Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture.
5. A Generic Network Interface Architecture for a Networked Processor Array (NePA).
6. Parallel FFT Algorithms on Network-on-Chips.
7. Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).
8. On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture.
9. Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform.
10. Parallel processing for block ciphers on a fault tolerant networked processor array.
11. Parallel FFT Algorithms on Network-on-Chips.
12. On Design and Application Mapping of a Network-on-Chip(NoC) Architecture.
13. Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router.
14. Design of a router for network-on-chip.
15. PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS
16. Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip
17. Self-optimized Routing in a Network on-a-Chip
18. Parallel FFT Algorithms on Network-on-Chips
19. A Generic Network Interface Architecture for a Networked Processor Array (NePA)
20. Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture
21. Fixed-point analysis and simulations of AC-3 algorithm
22. Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform
23. Parallel processing for block ciphers on a fault tolerant networked processor array
24. Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router
25. Design of a router for network-on-chip
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