Search

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3-σ value of the phase skew from 4.16 to 2.25 ps.

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control.

A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various functions and circuits’ techniques are newly adopted to improve performance and power consumption compared with DDR4 SDRAM. First, to realize two times higher speed than DDR4, the injection-locked oscillator (ILO) delay locked loop (DLL) is adopted for the low jitter high-speed performance. The proposed DLL with phase rotator (PR) and ILO allows to minimize the clock tree of DRAM, lowering skew and jitter in the DRAM internal clock path. Second, for the high-speed write operation, DQS gate opening control and write leveling are very important to minimize the turnaround time of DRAM, and thus new sequence and logic for the write-level training are introduced in this article. Third, to maximize the data valid window of read DQs, duty cycle adjustable serialize circuit methods are proposed. Finally, to improve the interface speed, the decision feedback equalization (DFE) and feedforward equalization (FFE) are adopted to Rx and Tx, respectively. By implementing all the items mentioned earlier, the 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 achieved 6.4-Gb/s/pin performance at 1.05-V $V_{DD}$ , with its power bandwidth efficiency 30% higher than that of DDR4.

The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and temperature (PVT) variations in sub-nanometer DRAM process are required to improve performance. To achieve 24Gb/s/pin on a 1.35V DRAM process, this work proposes a GDDR6 DRAM with a half-rate clocking architecture and optimized I/O.

This paper introduces a physical layout design methodology that produces DRC-clean, area-efficient, and programmable layouts of digital circuits in advanced DRAM processes. The proposed methodology automates the layout generation process to enhance design productivity, while still providing rich customization for efficient area and routing resource utilizations. Process-specific parameterized cells (PCells) are combined with process-independent place-and-route functions to automatically generate area-efficient and programmable layouts. Routing grids are optimized to enhance the area and routing efficiency. The proposed method reduced the design time of digital layouts by 80% compared to a manual design with high layout qualities, significantly enhancing the design productivity.

There is enormous demand for high-bandwidth DRAM: in application such as HPC, graphics, high-end server and artificial intelligence. HBM DRAM was developed [1] using the advances in package technology: TSV, microbump and silicon-interposer. Owing to these advances, HBM has a much higher bandwidth, at a lower pin speed rate, than conventional DRAM. However, the 3D-stack structure causes TSV interface and PDN problems: TSV connection failure and 3D-accumulation of IR drop, which increases the total cost of HBM. Moreover, as memory bandwidth increases DRAM architectural challenges arise, power consumption and associated thermal problems increase as well.

This paper presents a compact resistor-based CMOS temperature sensor intended for dense thermal monitoring. It is based on an $RC$ poly-phase filter (PPF), whose temperature-dependent phase shift is read out by a frequency-locked loop (FLL). The PPF’s phase shift is determined by a zero-crossing (ZC) detector, allowing the rest of the FLL to be realized in an area-efficient manner. Implemented in a 65-nm CMOS technology, the sensor occupies only 7000 $\mu \text{m}~^{\mathrm{ 2}}$ . It can operate from supply voltages as low as 0.85 V and consumes 68 $\mu \text{W}$ . A sensor based on a PPF made from silicided p-poly resistors and metal–insulator–metal (MIM) capacitors achieves an inaccuracy of ±0.12 °C (3 $\sigma $ ) from −40 °Cto 85 °C and a resolution of 2.5 mK (rms) in a 1-ms conversion time. This corresponds to a resolution figure-of-merit (FoM) of 0.43 pJ $\cdot \text{K}~^{\mathrm{ 2}}$ .

Required system performance for the computing and server, cost and power forces DRAM to improve its bandwidth, capacity and power. DDR5 SDRAM has been proposed as the next memory solution, with various new functions and circuit techniques to overcome the limitation of DDR4. Speed has been increased to 4.4 – 6.4Gb/s from DDR4’s 3.2Gb/s. Energy efficiency has improved by over 30% using a $1.1\mathrm {V}\, V_{\mathrm {DD}}$ and a $1.8\mathrm {V}\, V_{\mathrm {PP}}$. To achieve the performance and power consumption targets DDR5 adopted a small number of command pins with 2cycle decoding, new write training methods, an on-die ECC, an un-matched DQ/DQS scheme, and an equalize scheme for the interface. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a high-speed circuit techniques using a 1.1V DRAM process.

Recently the demand for high-bandwidth graphic DRAM, for game consoles and graphic cards, has dramatically increased due to the development of virtual reality, artificial intelligence, deep learning, autonomous driving cars, etc. These applications require greater data transfer speeds than pervious devices, GDDR5 [1] and GDDR5X [2], which are limited to 12Gb/s/pin. This paper introduces an 8Gb GDDR6 operating at up to 16Gb/s/pin. To exceed the prior speed limit various bandwidth extension techniques are proposed. WCK is driven with a dividing scheme to overcome speed limitations and to reduce power consumption. In addition, a dual-band architecture with different types of nibble drivers is proposed in order to cover stability of CML-to-CMOS in all frequency regions; CML nibble is used for high-speed, while CMOS nibble is used for low-speed. A DC-split scheme is implemented for duty-cycle correction and skew compensation. The bandwidth of the high-frequency divider is extended by using a proposed mode-changed flip-flop. The receiver uses a loop-unrolled one-tap decision-feedback equalizer (DFE) designed to eliminate channel inter-symbol interference (ISI). A two-stage pre-amplifier is also used for bandwidth extension. The transmitter uses a 4:1 multiplexer using a half-rate sampler, where a 1UI pulse is unnecessary to minimize the full-rate operation. To secure on-chip signal transmission characteristic, the bandwidth limitation of transistor in a DRAM process is extended by adopting an on-chip feedback EQ filter.

The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consumption, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power consumption of a variable delay line by 30% by sharing a part of the delay line path in DLL. In addition, jitter is reduced by 45 ps in the 1066-DDR3 operating mode by MDCDL. The proposed DLL utilizes an or-and functioned duty cycle corrector (or-and DCC), which consumes 15% of DLL's power, 0.915 pJ/Hz at tCK=1.5 ns and VDD=1.575 V. The countered CAS latency controller (CCLC) saves IDD3N current because it does not need a DLL clock and does not need to be activated for IDD3N (active non-power down) state. The DLL clock is enabled and CCLC is activated only when the read command is issued. This operation condition saves the IDD3N current by 60% with the proposed DLL. The proposed DLL is employed in 128 M×8 DDR3 SDRAM and 64 M×16 DDR3 SDRAM. The former and the latter are fabricated by 5×nm and by 4× nm DRAM process technology, respectively. Experimental results show that ±10% duty error of the external clock can be corrected to within ±2% duty error in less than 512 cycles of locking time under 1.5 ns of tCK. The proposed DLL and CCLC can operate above 1.0-GHz operating frequency at 1.2 V in 5× nm DDR3 SDRAM and at 1.0 V in 4× nm DDR3 SDRAM, respectively. The proposed DLL fabricated with 4× nm technology consumes 6.1 pJ/Hz at 1.575 V.