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The realization of high interconnect densities for three-dimensional integration demands development of new wafer-to-wafer bonding approaches. Recently introduced Cu-to-Cu wafer-to-wafer hybrid bonding schemes overcome scaling limitations, but like other Cu-based interconnect structures, they are prone to electromigration. Migration and growth of voids, induced by electromigration and mechanical stress, cause Cu-to-Cu hybrid bonds to fail. A comprehensive modeling approach is required to fully understand the complex dynamics of voids with their influencing factors, such as current density, temperature, and mechanical stress. In this work, we utilize such a modeling approach to perform studies of void migration through Cu-to-Cu hybrid bonds. The calculated velocities of the evolving void surface fully correspond to the experimentally observed behavior of voids migrating from the lower pad to the upper diffusion barrier of the upper pad, where they cause electrical failure. The migration velocity of a void in the upper pad is 20% higher than the migration velocity of a void in the bottom pad. Unbalance of the normal velocity distribution at the void surface leads to the transformation of the originally ellipsoid void into a teardrop shape. The simulations provide full insight in the impact of layout geometry, material properties, and operating conditions on void dynamics. In addition, the results enable targeted adjustments of the influencing factors to inhibit void migration and growth in order to delay or to fully prevent Cu-to-Cu hybrid bond failure.

An effective method for the formation of a Zn-doped Ru liner is demonstrated that realizes a self-forming barrier to achieve low resistivity interconnects for future back-end of line interconnect nodes. The “Ru–Zn” exhibits significantly improved adhesion to the dielectric and better electrochemical nucleation as compared to those of pristine Ru. In addition, time-dependent dielectric breakdown (TDDB) measurements indicate the inhibition of Cu ions drifting into the dielectric that precedes the TDDB failure. Complementary analysis using x-ray absorption spectroscopy, transmission electron microscope, and energy dispersive spectroscope suggests that the “Ru–Zn” forms an interfacial Zn–Si–O compound, and Zn, being more electronegative than Cu, protects the latter from oxidation. Calculation using density function theory also indicates that the Zn–Si–O compound adopts an intercalated structure at the interface of Ru/dielectric in which Zn occupies the interstitial sites within the Si–O lattice. We propose a twofold mechanism for improved TDDB performance: (1) the intercalated Zn atoms effectively block the diffusion of Cu ions through the dielectric and (2) Zn provides the cathodic protection of Cu that prevents the generation of mobile Cu ions that accelerate the TDDB.

The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a resistance ~2x higher than Co when a 1.1 nm titanium nitride (TiN) film, realized by atomic layer deposition (ALD), was used as an adhesion/nucleation layer. The lowest SV resistance of 56 Ω at the median was obtained with 0.3 nm of titanium oxide (TiOx) ALD and Ru CVD. This configuration gave a 3.4x lower resistance than the equivalent scheme with 0.3 nm TiN ALD and 15% lower resistance than the stacked-via configuration (with 0.3 nm TiOx and Ru fill), meaning that an IR-drop penalty is avoided when compared to the stacked-via approach. A congestion reduction can also be expected from the CD reduction of the SVs as the exclusion area in the intermediate layer can be smaller. Thermal shock tests for both Ru and Co SVs produced no failure after 1000 cycles between −50 °C and 125 °C, and 250 hours.

We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO 2 , LK3.0, SiCO and Si 3 N 4 films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO 2 , LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si 3 N 4 films.

For the first time a non-invasive localisation of a soft breakdown (SBD) is shown. The localisation is completed on fully functional back end of line (BEOL) test structures. The test structures used, provided by the interuniversity microelectronics centre (imec), are metal insulator semiconductor (MIS) structures. The low k dielectric within the test structures is SiOCH type with OSG 2.0 (k = 2.0), 45% porosity and 40 nm thickness. Contacless faul isolation methods have been evaluated for detecting a SBD on these structures. We evaluated photon emission microscopy (PEM) with two different signal detectors, the Si - CCD and the InGaAs camera. A proof of concept for detecting a SBD with themal laser stimulation (TLS) is presented. Using a Si - CCD and up to 2000 s integration time, photon emission (PE) signals from a 2 mm × 2 mm test structure with a leakage current less than 1 nA are presented. With the InGaAs detector a localised SBD from a 2 mm × 2 mm test structure with a leakage current of 100 pA is shown. The detected SBDs have a resistance of 33 GO and 260 GO respectively thus the level of degradation is several orders of magnitude lower compared to a hard breakdown (HBD). Up to now it was only possible to localise defects at higher levels of degradation. Due to the high energy at these levels, original defect signatures for SBD are usually destroyed. To better control the process of degradation, a way to nearly freeze the degradation process is shown. This method was used to detect a 1 nA leakage current of a 2 mm × 2 mm structure with a resistance of 35 GO using optical beam induced resistance change (OBIRCH) which is a similar contactless fault isolation (CFI) method to TLS. The presented SBD localisations allow to plan accurate physical preparations for the first time. Physical analysis of PEM localised SBD and HBD have been performed and compared. Possibilities to further improve the presented SBD detection levels are discussed for OBIRCH. Limitations for PEM with Si - CCD and InGaAs detectors as a CFI for SBDs are discussed.

We evaluate the reliability of a semidamascene BEOL scheme with direct metal etched (DME) Ruthenium and 16 nm wide air gaps (AG). First, we show that Ru can be barrierless independent of the type of deposition (ALD, CVD, PVD) using planar capacitor structures with a metal-etch-based flow. We present TDDB results of semidamascene Ru +AG showing V max to be above 1.5 V for TTF 0.1% of 3 km long lines at 100°C (using power law model). We show no change in resistance after >1200 h during electromigration tests at 330°C with 5 MA/cm2 stress. We identify increased Joule heating as a reliability concern.

We evaluate the reliability of Mo as word line metal for 3-D NAND Flash devices, by mimicking the stacked architecture using planar capacitors with SiO 2 /Al 2 O 3 and SiO 2 /HfO 2 dielectric stacks. By combining TDDB and TVS measurements with simulations, we show that Mo does not drift in the two examined stacks. Moreover, our study highlights the importance of controlling the defectivity at the SiO 2 /high-k interface and within the high-k to avoid the risk of early dielectric breakdown.

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.

Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.

Metal drift induced failure is a serious threat to the reliability of advanced back-end-of-line (BEOL) systems based on ultra-thin dielectric layers and metallization schemes with, at best, a very thin barrier. We evaluate the reliability of Cobalt (Co) and low-k dielectric (LK3.0) systems, with a focus on the impact of the metal/dielectric (m/d) interface and of barrier thickness and continuity. Our study confirms that metal drift is a surface driven phenomenon; in the case of low-k dielectrics, it is therefore crucial to preserve a hydrophobic m/d interface to minimize the occurrence of metal drift. Moreover, we find that, as the dielectric thickness is reduced, a thicker barrier is needed to prevent metal drift induced failure, regardless of the interface conditions. Nonetheless, we observed a sizeable increase of the intrinsic field acceleration factor, i.e. when no metal drift occurs, as dielectric thickness decreases, suggesting that scaled dielectrics are more resilient to intrinsic dielectric breakdown.

Patterns down to 21nm metal pitch (MP) have been used in the hybrid metallization scheme of Ru via prefill followed by a Cu trench metallization. The via resistance for Ru in hybrid with TaNRu/Cu trench fill is benchmarked to Co and Ru dual-damascene (DD) metallization schemes. At 30nm MP, a 40% via resistance reduction is observed upon introducing the Ru prefill prior to the Cu metallization. The Ru prefill significantly improved the via yield for the Cu metallization in 21nm MP. At this dimension, a 35% lower resistance is obtained with the Ru-Cu hybrid system when benchmarked to Co and Ru full fill with a 1nm TiN barrier. The electromigration of the Ru-Cu hybrid system does not a show a performance degradation, making it a viable scaling scenario for DD metallizations in N5 technologies and beyond.

We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a dense low-k and using a barrierless Ru fill scheme. We show our line-to-line and tip-to-tip TDDB pass 10 years of lifetime at 0.75 V for technology relevant line lengths and number of tips, respectively. Intrinsic dielectric breakdown without metal drift is demonstrated using BTS-TVS measurements. We also investigate the impact of dielectric scaling towards lower dimensions using planar capacitor structures. We observe an increasing field acceleration factor with decreasing thickness possibly suggesting different, slower, degradation mechanisms being present in the thinner dielectrics leading towards more reliability margin for scaled interconnects.

To achieve robust middle of line interconnects in advanced CMOS technology, electrical reliability of the dielectric stacks consisting of low-k spacer and nitride spacer dielectrics between gate metal and local interconnect metal is critical. To mimic this dielectric system, this work focuses on the stacks having SiN on top of SiO 2 with the total thickness below 15nm. The electrical conduction is proven to be determined by the electron injection interface. Additional defects are found in the SiN layer close to the SiO2 interface as the result of SiN deposition on SiO2. These defects assist electron transport when the electrons are injected from the SiN side. In the time dependent dielectric breakdown assessment, the Weibull slope, β, behaves differently under positively and negatively biased stresses where +β depends on both SiO 2 and SiN thicknesses, but -β is mainly dependent on the SiO 2 thickness and is only weakly dependent on the SiN thickness. The field acceleration factor, +m and -m, show similar relations versus the equivalent SiN thickness. Due to the much higher electric field distributed in the low-k layer in dielectric stacks, the performance of low-k spacer layer is proven to be crucial for the stack reliability.

The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions of minimum island, via extension and tip-to-tip (T2T). Five-track place and route (PNR) and SRAM constructions were realized with the self-aligned block (SAB) technique. Stacked vias showed resistance modulation with the size of the minimum island due to the change in via chamfer. High aspect ratio supervias (SV), to bypass M2 and directly link M1 to M3, were tested with different metallization schemes. Line-to-line and T2T reliability tests passed the 10- year lifetime predictions. Finally, electromigration (EM) tests on SV showed no failures after 140 hours of accelerated stress conditions.

We report a new non-destructive method to localize interconnection failures in 3-D devices. The scanning optical microscopy (SOM) technique is based on lock-in thermal laser stimulation (LI-TLS) and uses thermal waves to non-destructively map the current path in a 3-D device. We validate the method with test structures and show how the magnitude and phase of a propagating thermal wave may provide valuable 3-dimensional information on the failure location. We apply the technique on a short failed chain structure in a four level chip stack with an intensity modulated laser as a thermal wave injector and the structure under test as a detector. We confirm our results by physical failure analysis through a selective cross sectioning process.

Understanding the impact of process variability on TDDB is crucial for assuring robust reliability for current and future technology nodes. This work introduces a lifetime prediction model that considers local field enhancement to assess the combined impact of die-to-die spacing variability and line edge roughness. The model is applied to 16 nm half-pitch BEOL interconnects assuming either the power law or the root-E as field acceleration model and the impact on lifetime reduction is discussed. In comparison with the ideal case of a straight line with a nominal spacing of 16 nm, a 1-sigma spacing variation of 0.6 nm and 1-sigma LER of 1 nm leads to ~ 3 orders of magnitude lifetime reduction when assuming power-law whereas this value is ~ 1 order of magnitude when assuming root-E.

In this paper we discuss a new EM test methodology, based on low-frequency noise (LFN) measurements. The main advantages of LFN over the standard accelerated EM tests are that they are non-destructive, much faster, closer to operation conditions and provide more fundamental understanding. Using the LFN technique, we study the EM properties in sub-30 nm line-width Cu interconnects with various metallization schemes. Furthermore, the EM activation energies of alternative metal interconnects (Ru, Co, W) are studied by means of LFN measurements.

MIM planar capacitors with different spacer dielectrics (SiN, SiCO and SiCBN) of varying thickness deposited on a 2nm Hf02 gate dielectric, were fabricated to investigate the gate/spacer stack intrinsic electrical reliability performance. The polarity dependent leakage current of gate/spacer dielectric stacks is understood by employing band diagram analyses and simulations using the Ginestra™ software. The asymmetrical J-E characteristic of the Hf02/SiN dielectric stack is attributed to the presence of a high defect density in the Hf02/SiN interface region originating from the deposition process. On the other hand, the higher as-grown defect density in SiCO and SiCBN results in a symmetrical J-E characteristic. A low defect generation efficiency in the thin SiN stacks has been demonstrated using stress induced leakage current and charge to breakdown studies. The underlying mechanisms can be linked to a change in degradation mechanism from electronic excitation to electron induced vibrational excitation, which is valid for low defect density dielectric systems. To ensure low leakage currents and robust dielectric breakdown characteristics for ultra-thin spacer layers below 5nm, it is important to control defect densities below 1019cm−3ev−1in the film.

This paper provides a further understanding of soft breakdown (SBD) defects occurring in metal insulator metal (MIM) back end of line (BEOL) test structures with copper metallization and a low-k dielectric. Metal insulator semiconductor (MIS) test structures are utilised to take advantage of the infrared transparent backside of the silicon chip to directly access the low-k material. Transmission electron microscopy (TEM) images and scanning transmission electron microscope energy dispersive X-ray (STEM-EDX) analysis of localised SBD defects with a resistance of $250\mathrm{G}\Omega$ are shown. The temperature within the defective area during the SBD is estimated to be >802°C. A numerical solver program is used to simulate the thermal conditions. An energy density of at least $2\mathbf{E}14\ \ \mathbf{pW}/\boldsymbol{\mu} \mathbf{m}^{3}$ is required to generate the presented defect morphology. Similarities between photon emission measurements (PEM) on MIM and MIS test structures allow transferring findings made on MIS structures to MIM structures. Spectral photon emission measurements (SPEM) are presented as a means to monitor the low-k degradation.

Germanium-on-silicon is a widely used semiconductor stack in silicon photonics. Ge photodetectors require low dark currents to limit power consumption and their reliability is assessed by standardized tests. However, conduction and degradation mechanisms at different voltages and temperatures are not yet fully understood. In this paper, to define these mechanisms, we use wafer level tests to study degradation mechanisms in Ge vertical p-i-n photodetectors, where we found that stressing with a constant voltage and sensing with an I- V sweep is the best-suited test method for these devices. Degradation mechanisms, which influence dark currents during stress, are identified as defect generation and filling of (pre-existing) defects/traps. We also show that the activation energy of conduction is influenced by different mechanisms, namely Shockley-Read-Hall (SRH) and diffusion in combination with trap-assisted tunneling (TAT) and that knowledge of these conduction mechanisms can be used to identify degradation mechanisms.

Electromigration mechanisms of W-heaters with Cu connections at each line end to supply the current to the heater were studied. For making reliable lifetime estimates, a temperature profile is proposed based on infra-red (IR) microscopy, electromigration activation energies and failure location. For our structure, we show that the temperature of the void location is close to the ambient temperature and hence the lifetime prediction methodology should take this into account. Also, different test methodologies for this application are benchmarked, where we show that iso-thermal electromigration tests have only a limited impact on the lifetimes of our structures.

Mitigation of the degradation for down-scaled interconnects requires an in-depth understanding of the failure mechanisms of electromigration and, therefore, the development of adequate simulation models based on this understanding. We present a novel concept for modeling of nano-interconnect structures, the effective domain method, which describes the impact of grain boundaries and grain distribution on the nano-interconnect reliability and how this impact changes with down-scaling of the interconnect width. Furthermore, a simple and numerically efficient approach for modeling of void growth and its influence on nano-interconnect resistivity is presented. Both novel approaches are studied on timely nano-interconnect layouts and discussed in comparison to experimental results. The simulations based on the novel modeling concept predict the reduction of interconnect lifetime with increased temperature and the reduced linewidth, as observed in experiments.

We benchmark our 2D-model with existing ID-models [1-4] to assess the impact of LER on BEOL TDDB for spacing

Where the introduction of 3D stacked ICs offers opportunities for new and faster applications, the use of ultra-thin stacked Si dies leads to new reliability challenges. One such challenge is to cope with the thermo-mechanical stresses induced by mismatches in the Coefficient of Thermal Expansion between the different materials used for stacking and packaging such as Si, copper, overmoulds, laminates and underfills, amongst others. These stresses are a key-concern for today's 2D-technologies and are even more severe for 2.5/3D-stacking and -packaging technologies with high interconnect densities.

Metal drift induced dielectric failure is a critical concern in deeply scaled MOL and BEOL systems. To better understand the underlying physics, we investigated metal drift induced dielectric degradation using planar capacitors. Based on triangular voltage sweep results, failure is attributed to local metal filament formation and growth. Combined with an area scaling study, the time dependent dielectric breakdown measurements performed at different temperatures show that metal filament growth limits the failure times at high fields, while metal filament formation is more dominant at low fields. The influence of these two mechanisms on top of intrinsic dielectric degradation makes the collection of reliability data in a wide field and temperature test window inevitable for reliable lifetime predictions.

We are able to localize dielectric soft break downs (SBD) in porous low k materials with photon emission measurements. Up to now it was only possible to isolate hard breakdowns with several orders of magnitude higher leakage current than SBD level. This work presents soft breakdown localisations down to a leakage current level of 100pA (260GΩ) and less. The contactless and non-destructive fault isolation of soft breakdowns is an important step to plan physical analysis of the soft breakdowns. The test samples used were provided by the interuniversity microelectronics centre (IMEC). Differences between an InGaAs detector and a Si-CCD detector for photon emission measurements are presented in this work. A short evaluation for optical beam induced resistance change (OBIRCH) as an alternative contactless fault isolation method is given. For photon emission measurements with a Si-CCD detector, long integration times up to 2000s have been applied to detect emission from a leakage current of less than 1nA (33GΩ}). A way to nearly freeze the degradation for a long time is presented. Due to the noise of an InGaAs detector the integration time is limited to 100s. Use of a silicon solid immersion lens increases the numerical aperture and the detection sensitivity. Resulting in a detectable emission by a leakage current of 100pA (260GΩ}). Optical beam induced resistance change (OBRICH) was also evaluated as a contactless fault isolation method for localising defects in these dielectric structures. For the OBRICH leakage paths of resistances up to 1MΩ} had been found, which is orders of magnitude less sensitive than photon emission.

The failure time of low-k dielectrics during TDDB measurements consists of the time of percolation path formation and the time of percolation path growth. However, during conventional high voltage TDDB tests, percolation path growth is artificially enhanced due to local overstress. By both using a dedicated test vehicle, so-called p-caps, and damascene samples and by using controlled experiments, with a combined constant current and constant voltage stress approach, we focus on the understanding of the percolation path growth characteristics and on the quantification of the percolation path growth time. It is shown that the path growth time is not influenced by the original defect density in the low-k dielectrics and is only little impacted by temperature and dielectric thickness. The percolation path growth time passes 10 years at operating conditions in all the tested samples. We show that, in certain specific situations, this time can serve as an extra reliability margin for low-k dielectric TDDB. However, this margin might be reduced when multiple percolation paths grow at the same time.

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

The next generations of data centers require a scalable optical transceiver technology. In this paper we present a silicon photonics platform supporting single-channel data rates of 50Gb/s and above. Advanced process options include 50GHz GeSi electro-absorption modulators, high efficiency thermo-optic phase shifters with P-pi

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10 nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using Ileak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced EOX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.

Electromigration assessment and optimization of nano-interconnects is a complex task which ultimately demands an application of both experimental and modeling methods. The goal of this work is to introduce and discuss a modeling concept that is not unnecessarily complex and that can be optimally combined with experimental studies in order to assess the relative impact of different factors on interconnect reliability. The presented model and related modeling methodology are applied to a set of electromigration tests.

We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).

Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.

The replacement of a sacrificial template by gap-filling ultralow-k dielectric is studied as an alternative integration approach for Cu/low-k interconnects. The low-k curing processes induce severe damage to metallization structures, leading to detrimental electrical performance. Cu lines are passivated by a PECVD SiCN layer. Optimal yield can be restored, and promising electrical performance is demonstrated. Film shrinkage leads to low-k delamination in the trenches. By using multiple spin coating followed by soft bake, void free gap-filling structure is achieved.

© 2016 IEEE. A Soft Breakdown (SBD) phenomenon happening in porous low-k dielectrics during time dependent dielectric breakdown measurements was investigated. The early formation of local conductive paths was identified by monitoring leakage currents and capacitance data in the SBD phase. The nature of this conductive path was demonstrated to be related to intrinsic dielectric degradation. By comparing samples with different process conditions, we found that barrier metal penetration is an important root cause of SBD initiation. Our study of the voltage and temperature acceleration of the SBD phenomenon shows that these acceleration factors, m=22 and Ea=0.2eV, are at a reasonable level. However, further investigations on large size devices illustrate that the difference in barrier metal penetration depth between different samples could lead to a large decrease of Weibull slopes and degrade the overall reliability performance. Therefore, innovations of metal barrier deposition on porous low-k dielectrics to avoid barrier metal penetration are required for advanced technology nodes. ispartof: pages:3- ispartof: IEEE International Reliability Physics Symposium - IRPS vol:2016-September pages:3- ispartof: IEEE International Reliability Physics Symposium - IRPS location:Pasadena, CA USA date:4 Jan 2016 status: published