463 results on '"KURODA, TADAHIRO"'
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2. Epilogue: Super-Evolution
3. A Fertile Ground for Innovation: More Than Moore
4. Regaining Lost Ground: Game Changer
5. Structural Transformation: More Moore
6. Prologue: The Return of Spring
7. Wireless Interface Technologies for 3D IC and Module Integration
8. Wireless Interconnect in Electronic Systems
9. Connectivity in Electronic Packaging
10. Slashing IC Power and Democratizing IC Access for the Digital Age
11. A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum
12. Hydrophilic Bonding of SiO2/SiO2 and Cu/Cu using Sequential Plasma Activation
13. Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
14. Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application
15. A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
16. A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network
17. Micron-to-Submicron Cu electroplating in view of Agile-X LSI Chips Fabrication using Open Facility
18. Wireless Interconnect in Electronic Systems
19. Connectivity in Electronic Packaging
20. A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS
21. A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network
22. 1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS
23. A183.4-nJ/Inference 152.8-μW 35-Voice Commands Recognition Wired-Logic Processor Using Algorithm-Circuit Co-Optimization Technique
24. A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA
25. A 12.8-Gb/s 0.5-pJ/b Encoding-less Inductive Coupling Interface Achieving 111-GB/s/W 3D-Stacked SRAM in 7-nm FinFET
26. A Deep Metric Learning-Based Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion
27. High-Speed, Low-Power Emitter Coupled Logic Circuits
28. Vertical Link On/Off Control Methods for Wireless 3-D NoCs
29. 3-D NoC on Inductive Wireless Interconnect
30. A 12.8-Gbps 0.5-pJ/b Encoding-less Inductive Coupling Interface Using Clocked Hysteresis Comparator for 3D-stacked SRAM in 7-nm FinFET
31. Proximity Wireless Communication Technologies: An Overview and Design Guidelines
32. A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic
33. A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias
34. 3D-Stacked SRAM Using Near-Field Wireless Communication
35. Inductive Coupled Communications
36. Adaptive Circuit Technique for Managing Power Consumption
37. Body Biasing
38. A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
39. A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
40. An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique
41. Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format
42. Low-Power Digital Circuit Design
43. A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
44. Threshold-Voltage Control Schemes through Substrate-Bias for Low-Power High-Speed CMOS LSI Design
45. A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
46. A bonding-less 5-GHz RFID module using inductive coupling between IC and antenna
47. A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation
48. A 7-nm FinFET 1.2-TB/s/mm$^{2}$ 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
49. A 5-GHz 0.15-mm² Collision-Avoiding RFID Employing Complementary Pass-Transistor Adiabatic Logic With an Inductively Connected External Antenna in 0.18-μm CMOS
50. Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface
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