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Several academic/commercial types of research are being seen in a much-paced manner concerning the optimizing the 3-D ICs with the techniques of FP-Floor Planning by the ever-increasing human needs along with the advancements that we are exposed these days. In general, FPFloor Planning was nothing but the process of optimizing any appropriate parameters in the taken 3-D ICs against the suitable applications. It was usually done whenever there were huge counts of spares inside the IC in every layer present interiorly. Thus, this paper deals with the challenges of optimization in 3-D ICs by optimizing the TSV count, crosssectional area, and wire length and temperature with shuffled frog leaping, MFO-Moth Flame Optimization, and MVOMulti-Verse Optimization FP-Floor Planning methodologies, respectively. For any optimizing need arising in ICs, there will be some parameters or additional features that will be added to the circuit to facilitate the optimization. However, there might be some delay in the tasks depending on which the floor planning kind of optimization is done by optimization of several attributes like space, temperature, etc. This delay could be caused primarily because of operating the simulation operation with the CPU-Central Processing Unit rather than with GPUs-Graphical Processing Units. So, the usage of GPUs in any computational process could put forth a drastic time consumption (i.e.) running any tasks in CPU alone consumes times but using the GPUs along with the CPU utilization makes a huge time-related contribution to the task which is being executed. So, furthermore, the run time will be reduced if the introduction of GPUs-Graphical Processing Units takes place. Performance evaluation is made for the temperature and run/execution time specifically to prove the effectiveness of this proposed method improvisation in 3-D ICs. [ABSTRACT FROM AUTHOR]