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This paper presents a federated learning approach based on utilizing computational resources of the IoT edge devices for training deep neural networks. In this approach, the edge devices and the cloud server collaborate in the training phase while preserving the privacy of the edge device data. Owing to the limited computational power and resources available to the edge devices, instead of the original neural network (NN), we suggest to use a smaller NN generated using a proposed heuristic method. In the proposed approach, the smaller model, which is trained on the edge device, is generated from the main NN model. By the exploiting Knowledge Distillation (K D) approach, the learned knowledge in the server and the edge devices can be exchanged, leading to lower required computation on the server and preserving data privacy of the edge devices. Also, to reduce the knowledge transfer overhead on the communication links between the server and the edge devices, a method for selecting the most valuable data to transfer the knowledge is introduced. The effectiveness of this method is assessed by comparing it to state-of-the-art methods. The results show that the proposed method lowers the communication traffic by up to 250 × and increases the learning accuracy by an average of 8.9 % in the cloud compared to the prior K D -based distributed training approaches in CIFAR-10 dataset. [ABSTRACT FROM AUTHOR]

In this article, we present a main memory system for improving the lifetime and security of phase-change main memories. Storing encrypted data increases the bit-flip rates in memory cells, which adversely affects the lifetime of the phase-change memory cells. Thus, to improve the lifetime and security, the proposed system reduces the bit-flip rates by introducing two techniques. The first technique is a memory-side encryption which provides security against DIMM stealing attacks. To prevent unauthorized accesses, in this technique, the encrypted data are not saved in the main memory. As the second technique, we suggest an adaptive partial encryption approach, which makes use of behavior tracking of the application in the CPU side to minimize the latency overhead of the first technique. Additionally, it prevents the loss of data against application-based attacks. This technique uses a recurrent neural network (RNN) to do sequence classification and detect malicious applications. In addition, an auxiliary method, called periodic encryption (PE), which overcomes the security loss in some applications induced by the low accuracy of the employed neural network, is presented. The efficacy of the proposed method is evaluated using gem5 simulator and some benchmarks. Compared to DEUCE and Crypto-Comp methods, the results for the lifetime evaluation show an average bit-flip rate reduction of 11%. In addition, the security improvements against the DIMM stealing and application-based attacks are about 100% and 92.5%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an approach for distributing the deep neural network (DNN) training onto IoT edge devices is proposed. The approach results in protecting data privacy on the edge devices and decreasing the load on cloud servers. In addition, the technique may reduce the communication traffic between the cloud and the edge devices. Since the available resources in the edge devices are limited, in the proposed approach, we suggest a heuristic technique for generating a smaller network based on the main network in cloud. Next, by exploiting the knowledge distillation method, the knowledge of the main network is transferred to the generated small network. In this approach, small networks on the edge devices under different datasets are trained where some of their parameters are aggregated for updating the main network parameters on the cloud. The effectiveness of this approach is assessed with some state-of-the-art neural networks. Results show that the approach, the price of preserving the data privacy, is, on average, about 3.5% accuracy loss compared to the case when the network is trained on the cloud and all the datasets of the edge devices are available for training. [ABSTRACT FROM AUTHOR]

In this article, we present an energy-efficient approximate CGRA (X-CGRA). Instead of conventional exact arithmetic units, it employs configurable approximate adders and multipliers in the so-called quality-scalable processing elements (QSPEs). Furthermore, the structure and functionality of the other architectural components, like context memory, are modified based on the quality-scalable operating modes of the QSPEs. The quality reconfigurability of the X-CGRA makes it amenable for both error-resilient and nonresilient applications. To map the applications on the X-CGRA, a mapping technique is proposed that efficiently utilizes the QSPEs and selects appropriate approximation modes in order to lower the energy consumption while satisfying a user-defined quality constraint. We evaluate the efficacy of our X-CGRA for several benchmark applications from different domains, including image/video processing, signal processing, and scientific computations. Different sizes of X-CGRA are synthesized using a 15-nm FinFET technology. For these benchmarks, the results indicate energy consumption reduction of up to 3.21 × compared to those of a typical exact CGRA, at the cost of 4% quality loss. [ABSTRACT FROM AUTHOR]

Thermal stress including temperature gradients in time and space, as well as thermal cycling, influences lifetime reliability and performance of modern multiprocessor systems-on-chip (MPSoCs). Conventional power and temperature management techniques considering the peak temperature/power consumption do not provide a comprehensive solution to avoid high spatial and temporal thermal variations. This work presents TheSPoT, a novel multilevel thermal stress-aware power and thermal management approach for MPSoCs. At the top level, core consolidation and deconsolidation is performed based on peak temperature, thermal stress, and power consumption constraints. These constraints are also used at the next level, where operating frequencies are determined. At this level, we obtain optimal core frequencies by solving a convex optimization problem. However, thereafter, to reduce the runtime overhead in large MPSoCs, we alternatively propose to use a fast heuristic algorithm. The efficacy of the proposed approaches in reducing the thermal cycles and temporal/spatial temperature gradients is evaluated by comparing the results with the state-of-the-art methods. The evaluation performed on 4-core, 8-core, and 16-core MPSoCs, using PARSEC benchmarks, reveals a considerable reduction in thermal stress. For the 8-core MPSoC case study, on average, for the proposed heuristic(optimal) approach, the mean time to failure improved by 47(35)% compared to the state-of-the-art techniques with only 6(4)% performance degradation. Also, our simulations show that TheSPoT is more efficient in thermal stress reduction when more heterogeneous workloads are used. [ABSTRACT FROM AUTHOR]

In this paper, we present an accuracy-aware operating voltage management unit to improve the lifetime of processors by considering the error-resilient nature of some applications. This unit is placed in the power management unit of the processor and its operation is based on the aggressive operating voltage reduction during the runtime of error resilient applications. This unit determines the operating voltage of the processor based on the type of the running application, the predefined minimum acceptable quality, and the operating voltage level specified by the dynamic voltage frequency scaling controller of the processor power management unit. The determined operating voltage by this unit results in lifetime improvement and power reduction at the cost of timing violations that are tolerable by error-resilient applications. In addition, the proposed unit dynamically adjusts the minimum acceptable operating voltage based on the impact of aging mechanisms. The aging mechanisms considered in this work include Negative Bias Temperature Instability, Hot Carrier Injection, Time Dependent Dielectric Breakdown, Thermal Cycling, Electro-Migration, and Stress Migration. The efficacy of the proposed operating voltage management is investigated by applying it to some exact and error-resilient applications. The results show that the proposed unit lead to, on average, 38.82% lifetime improvement as well as 41.8% power consumption reduction. [ABSTRACT FROM AUTHOR]

In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a c arry- l ookahead and c arry- p ropagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required. [ABSTRACT FROM AUTHOR]

In this work, to increase the reliability of low power digital circuits in the presence of soft errors, the use of both III-V TFET- and III-V MOSFET-based gates is proposed. The hybridization exploits the facts that the transient currents generated by particle hits in TFET devices are smaller compared to those of the MOSFET-based devices while MOSFET-based gates are superior in terms of electrical masking of soft errors. In this approach, the circuit is basically implemented using InAs TFET devices to reduce the power and energy consumption while gates that can propagate generated soft errors are implemented using InAs MOSFET devices. The decision about replacing a subset of TFET-based gates by their corresponding MOSFET-based gates is made through a heuristic algorithm. Furthermore, by exploiting advantages of TFETs and MOSFETs, a hybrid TFET-MOSFET soft-error resilient and low power master-slave flip-flop is introduced. To assess the efficacy of the proposed approach, the proposed hybridization algorithm is applied to some sequential circuits of ISCAS’89 benchmark package. Simulation results show that the soft error rate of the TFET-MOSFET-based circuits due to particle hits are up to 90% smaller than that of the purely TFET-based circuits. Furthermore, energy and leakage power consumptions of the proposed hybrid circuits are up to 79% and 70%, respectively, smaller than those of the MOSFET-only designs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a modified carry select adder (CSLA) structure which is more power/energy and area-efficient compared to the existing CSLAs. The higher efficiency is achieved by modifying the logic formulations of the carry generation and selection (CGS) scheme and merging all of its redundant logic operations in the carry generation (CG) and carry selection (CS) units of the CGS-based CSLA (CGS-CSLA) structure. This leads to a simplified structure. Next, the proposed CSLA structure is employed to design efficient square-root CSLA (SQRT-CSLA) structure. The efficiency of the proposed SQRT-CSLA is investigated by comparing its speed, power, energy, and area parameters with those of some other SQRT-CSLA structures, including conventional SQRT-CSLA, binary to excess-1 converter, common Boolean logic, and the CGS-based SQRT-CSLA structures. The investigation, which is performed using HSPICE simulations based on a 45 nm bulk CMOS technology, includes 8, 16, 32, and 64-bit adder structures. The impact of voltage scaling on the efficiency of the proposed structure is also studied by changing the supply voltage levels from the near-threshold voltage to the nominal supply voltage. Simulation results reveal that the proposed SQRT-CSLA provides, at least, 14%, 14%, and 15% lower energy, energy-delay product, and area-delay product, respectively, compared to those of the CGS-based SQRT-CSLA structure, averaged over the supply voltage and bit length. [ABSTRACT FROM AUTHOR]

In this paper, the impact of physical parameter variations on the electrical characteristics of III-V TFETs is investigated. The study is performed on the operations of two optimized ultra-thin 20 nm double-gate transistors. The two device structures are InAs homojunction TFET and InAs-GaAs 0.1 Sb 0.9 heterojunction TFET. The operation parameters are the ON-current, OFF-current, and threshold voltage. The investigation is performed at the device level, using a device simulator and the Monte-Carlo simulation approach is exploited to extract the distribution of electrical parameters in the presence of the process variation. The results reveal that the operation of the transistor is more sensitive to the doping of the source and gate work function compared to other physical parameters. Furthermore, the heterojunction TFETs show less sensitivity to physical parameter variations compared to the homojunction ones. [ABSTRACT FROM AUTHOR]

In this paper, we propose a single probability density function for the distributions of the delay in the presence of the process variation for different regions of operation. The delay variation model is inspired by considering the analytical current models for each operating region. Based on these models, we suggest using the log-skew-normal distribution for modeling the delay variation for a wide range of supply voltages from the subthreshold to above-threshold regions. To assess the accuracy of the proposed delay distribution, the mean, standard deviation, skewness, 99th percentile, and yield of the proposed distribution are compared with those of the normal and log-normal distributions using the Monte Carlo (MC) simulations for different circuits in both bulk and FinFET technologies. The results show a higher accuracy for the proposed distribution in all regions of operation. Also, the proposed model enables us to obtain the 3 \sigma yield of the distribution using up to 3.4 times less MC simulation time. [ABSTRACT FROM PUBLISHER]

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints. [ABSTRACT FROM AUTHOR]

This paper presents an efficient temperature dependent hot carrier injection reliability simulation flow which is scalable. The flow makes use of some efficient techniques at different design hierarchical levels to enable full chip simulation with a fast run time and high enough accuracy. While the transistor-level HCI effect is modeled based on the conventional reaction–diffusion (R–D) framework, the gate-level characterization method combines HSpice simulation and piecewise linear curve fitting to model the impact of HCI effect over the time. Also, as one of the ways to improve the speed of the simulation, only the NMOS transistors, which suffer much more from the HCI effect, are considered in the modeling. In addition, among these devices, only those which are more significantly affected are included. For each cell, only the transitions which induce the HCI impact are included. Finally, to improve the efficiency of the circuit simulation, logic cells in the circuit are classified into two groups of critical and non-critical where the critical (non-critical) ones are simulated using fine (coarse) granularity simulation time steps. The proposed method reduces the simulation time without losing much of accuracy. Also, due to the considerable impact of the temperature on the reliability, at all levels of the proposed simulation flow, the impact of the temperature on the impact of the HCI phenomena is modeled. The simulations performed on some benchmarks reveal that the proposed circuit-level HCI modeling is able to reduce the runtime of calculating the threshold voltage and mobility drifts of the gates significantly without sacrificing accuracy unacceptably. Also, the circuit-level simulations indicate an about 19% increase in the average of the HCI-induced delay degradation of the benchmarks when the temperature rises from 20 °C to 100 °C. [ABSTRACT FROM AUTHOR]

In this paper, a locality aware NoC communication architecture is proposed. The architecture may reduce the energy consumption and latency in MultiProcessor Systems on Chips (MPSoCs). It consists of two network layers which one layer is dedicated to the packets transmitted to near destinations and the other layer is used for the packets transmitted to far destinations. The actual physical channel width connecting the cores is divided between the two layers. The locality is defined based on the number of hops between the nodes. The relative significances of the two types of communications determine the optimum ratio for the channel width division. To assess the efficiency of the proposed method, we compare its communication latency with that of conventional one for different channel widths, communication traffic profiles, and mesh sizes. [ABSTRACT FROM AUTHOR]

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows. [ABSTRACT FROM AUTHOR]

In this paper, we present techniques for mitigating the Negative Bias Temperature Instability (NBTI) effect on extensible processors. Firstly, the effect of NBTI on the extended instruction set architecture and the arithmetic logic unit of extensible processors is studied. The study includes modeling the circuit delay increase due to the NBTI and analyzing its impact on the processor lifetime. The study shows that in some cases, the lifetime is decreased while in other cases, it is increased compared to that of a baseline processor. Next, to lower the impact of the NBTI on the extensible processor lifetimes, we present four different techniques. The first technique is based on injecting proper input vectors during the idle time of the custom instructions such that the NBTI effect is reduced. The lifetime improvement, however, is limited by the delay increase reduction of the applied input vectors. In the second technique, the guard band delay of extensible processor is extended. This is effective because the rate of lifetime increase due to extending the guard band delay is much higher than the rate of speedup reduction. For the third technique, we duplicate the critical custom instructions to increase the processor lifetime without losing any speedup. The last technique estimates the delay increase of candidate custom instructions (CIs) and selects those that do not reduce the lifetime. The efficacies of the aforesaid techniques are evaluated and compared against each other by using benchmarks from different application domains. [ABSTRACT FROM AUTHOR]

In this work, we propose a clock skew-aware aging mitigation (CSAM) technique which considers the effect of asymmetric aging both on logic path and clock tree together. Simultaneous consideration of both parts in the design optimization problem enables us to reduce the area overhead while increasing the lifetime. For the aging mitigation of the logic path, we make use of both internal node control (INC) and input vector control (IVC) techniques while, for the clock tree circuits, a proper choice between NAND or NOR based integrated clock gating (ICG) cell is made. The optimization may be performed based on two objective functions of maximizing lifetime or minimizing the area overhead for a predetermined clock frequency and lifetime. To assess the efficacy of the proposed technique, we compared the lifetimes and area overheads for a set of circuits from ISCAS89 and ITC99 benchmark suites when CSAM and conventional techniques are used. The results, obtained using SPICE simulations for the circuits in a 45-nm technology, reveals that an average lifetime improvement of 34% and an average area overhead reduction of 25.7% for the two objective functions, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an approach for incorporating the effect of various logic synthesis options and logic level implementations into the custom instruction (CI) selection for extensible processors. This effect translates into the availability of a piecewise continuous spectrum of delay versus area choices for each CI, which in turn influences the selection of the CI set that maximizes the speedup per area cost (SPA) metric. The effectiveness of the proposed approach is evaluated by applying it to several benchmarks and comparing the results with those of a conventional technique. We also apply the methodology to the existing serialization algorithms aimed at relaxing register file constraints in multi-cycle custom instruction design. The comparison shows considerable improvements in the speedup per area compared to the custom instruction selection algorithms under the same area-budget constraint. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we present a technique for custom instruction (CI) extension considering process variations. The technique bridges the gap between the high level custom instruction extension and chip fabrication in nanotechnologies. In particular, instead of using the conventional Static Timing Analysis (STA), it utilizes Statistical Static Timing Analysis (SSTA). Therefore, the approach becomes probabilistic where the delay of each CI is modeled by a Probability Density Function (PDF). Using this probabilistic approach, different subsets of the CIs extension are identified to meet predefined constraints (identification phase) and eventually selected for realization to improve a given merit function (selection phase). In the identification phase, performance yield under both random and systematic variations is added as a constraint. Also, a pruning technique is proposed to decrease the runtime of the systematic variation modeling. The results show that the technique reduces the number of the CIs which need systematic variation modeling by about 24.6% for the cases studied in this work. In the selection phase, both greedy and branch-and-bound approaches are used. In the greedy approach, the conventional merit function based on the cycle saving and area is modified to include the performance yield. The results show the proposed merit function leads to about 3.2% increasing in the speedup. In the branch-and-bound method an effective pruning technique is described to reduce the runtime. The pruning technique is able to reduce the search space about 62%. [Copyright &y& Elsevier]

Abstract: Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of the control bits, it finds partitions with similar transition behaviors and groups them together. One extra control bit is added to each group of partitions. Properly managing number of transitions on control bits of each partition and that of each group, GPH reduces total power consumption, including coupling power. It also locates control bits of each partition such that total power consumption is minimized. We evaluate the efficiency of the proposed method for coding data and address buses under various hardware platforms. Experimental results show 43% average power saving in coded data compared to the original one. We also show the prominence of our coding scheme over previously proposed techniques. [Copyright &y& Elsevier]

In this paper, we present an accuracy-aware design framework [called accuracy-aware high-level synthesis (Achilles)], which synthesizes a high-level description of an input application with the objective of minimizing the energy consumption of the synthesized circuit. The proposed framework includes two main parts of Achilles and light-weight predictor selection. The framework leverages light-weight error predictors (i.e., machine learning-based classifiers) to achieve more energy reduction by dynamically managing the output quality level (exact or approximate) of the synthesized circuit. To synthesize the input application, first, we exploit a heuristic algorithm to determine the quality level required for each operation in the data flow graph (DFG) representation of the input application. Next, for synthesizing the input application, we propose an effective Achilles algorithm which utilizes the flexibility of the available multiquality arithmetic units in a high-level cell library to synthesize the datapath. To improve the efficiency, the process starts by iteratively reducing the number of functional units required for synthesizing the DFG. Then, a proper light-weight error predictor satisfying the user expected quality is chosen from the available predictors in the framework. Based on the quality requirements, three different quality management modes are considered. The efficacy of the proposed framework is assessed for benchmarks from image and signal processing as well as robotics domains. The study of these benchmarks indicates that Achilles may reduce the energy consumption up to 51% (36% on average), up to 72% (51% on average), and up to 57% (33% on average) in threshold, average, and hybrid modes, respectively, for the studied cases. Moreover, the results show that relative coverage of large errors may be increased from 21% to 55% by employing synthetic minority oversampling technique method. [ABSTRACT FROM AUTHOR]

In this paper, we propose an energy efficient approximate multiplier design obtained by truncating the input operands. In the structure, the n-bit multiplication operation is transformed to a smaller bit length multiplication plus some add and shift operations. The simple calculation core makes the multiplier a scalable yet low power structure. Also, we suggest an output quality-tunable multiplier providing ability to change the output quality during the multiplication operation. The characteristics of the proposed multiplier are compared with those of the exact and some other approximate multipliers in a 45 nm technology. The comparison reveals an average improvement of 89.2% (74.9%) in terms of the energy (area) compared to that of the exact multiplier. The utility of the proposed multiplier in a JPEG encoder application is also investigated. The results reveal that the Peak Signal to Noise Ratio (PSNR) reduction is at most 0.15 dB compared to that of the exact one. [ABSTRACT FROM AUTHOR]

In this paper, we propose a training framework for an inverter-based memristive neuromorphic hardware. The framework, which is called PHAX, is a physical characteristics aware one relying on an ex-situ training approach. The considered neuromorphic circuit is highly energy efficient hybrid CMOS-memristive implementation of neuromorphic circuits. To solve the problem of high sensitivity of the training to the mismatches between the high-level mathematical modeling of the neurons and the corresponding physical characteristics, an approach for analytical yet accurate modeling of the memristive crossbar and neuron circuits is suggested. The approach, which is based on SPICE simulations, models the inverter-based neurons using a hyperbolic tangent function. To increase the training efficacy, the backpropagation training algorithm is modified by considering some constraints based on the physical characteristics of the memristive circuit. This modification along with the accurate back-annotation of the physical characteristics considerably improve the effectiveness of the ex-situ training method of the neuromorphic circuit. The results of this paper show an average reduction of $1805{\times }$ in the training runtime compared to that of the in-situ training approach. Furthermore, the results of applying the approach on the kernels of some applications such as image recognition, image processing, and financial analysis reveal that the designed neuromorphic circuits provide an average power saving (speed up) of $1478{\times }$ ( $5.2{\times }$ ) over the ASIC implementation in a 90-nm CMOS technology. [ABSTRACT FROM AUTHOR]