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1. A Ferroelectric Compute-in-Memory Annealer for Combinatorial Optimization Problems

2. Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security

3. Direct S-matrix calculation for diffractive structures and metasurfaces

6. Design and Characterization of a Variable Gain D-Band LNA for Optimized Link Budgeting for a 6G Receiver in 22FDX

7. On the Challenges and Design Mitigations of Single Transistor Ferroelectric Content Addressable Memory

9. Multilevel Operation of Ferroelectric FET Memory Arrays Considering Current Percolation Paths Impacting Switching Behavior

10. 1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation.

11. 28 nm HKMG-Based Current Limited FeFET Crossbar-Array for Inference Application

12. Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array

18. Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications

23. Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer

24. Integration of BEoL Compatible 1T1C FeFET Memory Into an Established CMOS Technology

29. Impact of Temperature on Reliability of MFIS HZO-based Ferroelectric Tunnel Junctions

30. Optimizing Ferroelectric and Interface Layers in HZO-Based FTJs for Neuromorphic Applications

35. A 2-Transistor-2-Capacitor Ferroelectric Edge Compute-in-Memory Scheme With Disturb-Free Inference and High Endurance

39. Impact of the Nonlinear Dielectric Hysteresis Properties of a Charge Trap Layer in a Novel Hybrid High-Speed and Low-Power Ferroelectric or Antiferroelectric HSO/HZO Boosted Charge Trap Memory

44. Design and fabrication of stacked, computer generated holograms for multicolor image generation

45. Investigation of the polarization-dependent diffraction of deep dielectric rectangular transmission gratings illuminated in Littrow mounting

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