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In this paper, we presented a method of minimizing the number of overlapped partial products in the accumulation of four-term Karatsuba multiplication. This method reduced the summation of 13 overlapped partial products to 9 and the summation of 40 overlapped partial products to 24 in the case of four-term Karatsuba multiplication and eight-term Karatsuba multiplication, respectively. Moreover, to deal with the problem of negative multiplicands introduced by the choice in the evaluation of four-term Karatsuba multiplication, we further presented a method of converting negative multiplicands to non-negative multiplicands. In this way, our method would lead to the reduction of summation complexity and not using signed multipliers. Compared to the original Karatsuba multiplication designs, our proposed Karatsuba-like multiplication with optimal interpolation would lead to up to 7.7% reduction in ADP (area-delay-product) in ASIC implementations, and up to 20.2% reduction in ADP compared with built-in designs of Synopsys Design Compiler.

Being able to detect program runtime complexity is useful in many tasks (e.g., checking expected performance and identifying potential security vulnerabilities). In this work, we introduce a new dynamic approach for inferring the asymptotic complexity bounds of recursive programs. From program execution traces, we learn recurrence relations and solve them using pattern matching to obtain closed-form solutions representing the complexity bounds of the program. This approach allows us to efficiently infer simple recurrence relations that represent nontrivial, potentially nonlinear polynomial and non-polynomial, complexity bounds. We present Dynaplex, a tool that implements these ideas to automatically generate recurrence relations from execution traces. Our preliminary results on popular and challenging recursive programs show that Dynaplex can learn precise relations capturing worst-case complexity bounds (e.g., O ( n log n ) for mergesort, O (2 n ) for Tower of Hanoi and O ( n 1.58 ) for Karatsuba’s multiplication algorithm).

The article reproduces the text of lectures on the life and work of the Soviet Academician I. M. Vinogradov, the first director of the Steklov Mathematical Institute of the Academy of Sciences of the USSR, delivered by his colleague and co-author A. A. Karatsuba (1937–2008) in September 1983 at the Tajik State University named after V. I. Lenin (now Tajik National University), Dushanbe.

In this brief, we proposed a highly-optimized FPGA-based implementation of the Ed448 digital signature algorithm. Despite significant progress in elliptic curve cryptography (ECC) implementations, Ed448 hardware architecture, to the best of our knowledge, has not been investigated in the literature. In this work, we demonstrate a high throughput while maintaining low resource architecture for Ed448 by employing a new combined algorithm for refined Karatsuba-based multiplier with precise scheduling. Furthermore, a compact distributed memory unit is developed to increase speed while keeping the area low. Our variable-base-point Ed448 architecture performs 327 signatures and 189 verifications per second at a notably higher security level of 224 bits, using not more than 6,617 Slices and 16 DSPs on a Xilinx Artix-7 FPGA. We also proposed possible countermeasures and extensions to Ed448 to counter the physical attacks.

As quantum computers become more affordable and commonplace, existing security systems that are based on classical cryptographic primitives, such as RSA and Elliptic Curve Cryptography ( ECC ), will no longer be secure. Hence, there has been interest in designing post-quantum cryptographic ( PQC ) schemes, such as those based on lattice-based cryptography ( LBC ). The potential of LBC schemes is evidenced by the number of such schemes passing the selection of NIST PQC Standardization Process Round-3. One such scheme is the Crystals-Dilithium signature scheme, which is based on the hard module-lattice problem. However, there is no efficient implementation of the Crystals-Dilithium signature scheme. Hence, in this article, we present a compact hardware architecture containing elaborate modular multiplication units using the Karatsuba algorithm along with smart generators of address sequence and twiddle factors for NTT, which can complete polynomial addition/multiplication with the parameter setting of Dilithium in a short clock period. Also, we propose a fast software/hardware co-design implementation on Field Programmable Gate Array ( FPGA ) for the Dilithium scheme with a tradeoff between speed and resource utilization. Our co-design implementation outperforms a pure C implementation on a Nios-II processor of the platform Altera DE2-115, in the sense that our implementation is 11.2 and 7.4 times faster for signature and verification, respectively. In addition, we also achieve approximately 51% and 31% speed improvement for signature and verification, in comparison to the pure C implementation on processor ARM Cortex-A9 of ZYNQ-7020 platform.

Lattice-based cryptography (LBC) is one of the promising post-quantum candidates which offers good security and performance. The most time consuming operations in LBC is the polynomial multiplication, which can be performed through widely explored algorithms like schoolbook polynomial multiplication algorithm (SPMA) and Number Theoretic Transform (NTT). However, Karatsuba algorithm with better complexity compared to SPMA, is not widely studied for FPGA implementation of LBC. In this brief, we proposed an optimized SPMA-Karatsuba (SK) architecture with novel technique to implement the negacyclic convolution. The proposed architecture is more than $2.09\times $ faster in expense of 96.06% additional hardware resources compared to the state-of-the-art SPMA architecture. This shows that the combination of SPMA and Karatsuba algorithm can produce hardware architecture with higher speed yet maintain balanced area-time efficiency compared to SPMA-only architecture. This is especially useful for developing IoT edge nodes or gateway devices that require high speed but able to tolerate some additional hardware area.

Within the transport layer security (TLS) protocol version 1.3, RFC 7748 specifies elliptic curves targeted at the 128-bit and the 224-bit security levels. For the 128-bit security level, the Montgomery curve Curve25519 and its birationally equivalent twisted Edwards curve Ed25519 are specified; for the 224-bit security level, the Montgomery curve Curve448, the Edwards curve Edwards448 (which is isogenous to Curve448) and another Edwards curve which is birationally equivalent to Curve448 are specified. Our first contribution is to provide the presently best known 64-bit assembly implementations of Diffie–Hellman shared secret computation using Curve25519. The main contribution of this work is to propose new pairs of Montgomery–Edwards curves at the 128-bit and the 224-bit security levels. The new curves are nice in the sense that they have very small curve coefficients and base points. Compared to the curves in RFC 7748, the new curves lose two bits of security. The gain is improved efficiency. For Intel processors, we have made different types of implementations of the Diffie–Hellman shared secret computation using the new curves. The new curve at the 128-bit level is faster than Curve25519 for all types of implementations that we considered, while the new curve at the 224-bit level is faster than Curve448 using 64-bit sequential implementation using schoolbook multiplication, but is slower than Curve448 for vectorized implementation using Karatsuba multiplication. Overall, the new curves provide good alternatives to Curve25519 and Curve448.

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area–delay product indicating the efficiency of design.

Saber, the only module-learning with rounding-based algorithm in NIST’s third round of post-quantum cryptography (PQC) standardization process, is characterized by simplicity and flexibility. However, energy-efficient implementation of Saber is still under investigation since the commonly used number theoretic transform can not be utilized directly. In this manuscript, an energy-efficient configurable crypto-processor supporting multi-security-level key encapsulation mechanism of Saber, is proposed. First, an 8-level hierarchical Karatsuba framework is utilized to reduce degree-256 polynomial multiplication to the coefficient-wise multiplication. Second, a hardware-efficient Karatsuba scheduling strategy and an optimized pre-/post-processing structure is designed to reduce the area overheads of scheduling strategy. Third, a task-rescheduling-based pipeline strategy and truncated multipliers are proposed to enable fine-grained processing. Moreover, multiple parameter sets are supported in LWRpro to enable configurability among various security scenarios. Enabled by these optimizations, LWRpro requires 1066, 1456 and 1701 clock cycles for key generation, encapsulation, and decapsulation of Saber768. The post-layout version of LWRpro is implemented with TSMC 40 nm CMOS process within 0.38 mm2. The throughput for Saber768 is up to 275k encapsulation operations per second and the energy efficiency is 0.15 uJ/encapsulation while operating at 400 MHz, achieving nearly $50\times $ improvement and $31\times $ improvement, respectively compared with current PQC hardware solutions.

Applications such as public-key cryptography are critically reliant on the speed of modular multiplication for their performance. This paper introduces a new block-based variant of Montgomery multiplication, the Block Product Scanning (BPS) method, which is particularly efficient using new 512-bit advanced vector instructions (AVX-512) on modern Intel processor families. Our parallel-multiplication approach also allows for squaring and sub-quadratic Karatsuba enhancements. We demonstrate $$1.9\,\times $$ 1.9 × improvement in decryption throughput in comparison with OpenSSL and $$1.5\,\times $$ 1.5 × improvement in modular exponentiation throughput compared to GMP-6.1.2 on an Intel Xeon CPU. In addition, we show $$1.4\,\times $$ 1.4 × improvement in decryption throughput in comparison with state-of-the-art vector implementations on many-core Knights Landing Xeon Phi hardware. Finally, we show how interleaving Chinese remainder theorem-based RSA calculations within our parallel BPS technique halves decryption latency while providing protection against fault-injection attacks.

The main objective is to develop floating-point multiplication (FPM) using 5:3 compressor based Vedic multiplier (VM), Karatsuba algorithm (KA) and canonical signed digit (CSD) algorithm to overcom...

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce's demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

We obtain new bounds of exponential sums modulo a prime $p$ with binomials $ax^k + bx^n$. In particular, for $k=1$, we improve the bound of Karatsuba (1967) from $O(n^{1/4} p^{3/4})$ to $O\left(p^{3/4} + n^{1/3}p^{2/3}\right)$ for any $n$, and then use it to improve the bound of Akulinichev (1965) from $O(p^{5/6})$ to $O(p^{4/5})$ for $n | (p-1)$. The result is based on a new bound on the number of solutions and of degrees of irreducible components of certain equations over finite fields.

We continue the study of Mastrovito form of Karatsuba (MK) multipliers under the shifted polynomial basis (SPB). An MK multiplier utilizes Karatsuba algorithm and Mastrovito approach to optimize polynomial multiplication and modular reduction, which lead to a better space and time tradeoff for all trinomials. Based on this work, we make two types of contributions: 1) We derive a new modular reduction formulation for constructing Mastrovito matrix associated with special types of pentanomials, i.e., Types I, II, and Type C.1 pentanomial. Through related formulations, we demonstrate that Type I pentanomial is less efficient than Type II because of a more complicated modular reduction under the same SPB; conversely, Type C.1 pentanomial is as good as Type II under generalized polynomial basis (GPB). 2) We introduce a new MK multiplier for Type II pentanomial. It is shown that our proposal is only one $T_{X}$ slower than the fastest quadratic multipliers for Type II pentanomial, but its space complexity is roughly 3/4 of those schemes. To the best of our knowledge, it is the first time for hybrid multiplier to achieve such a time delay bound.

Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers. We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice. Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor.

Multiplication is an essential step in a lot of calculations. In this paper we look at multiplication of 2 binary polynomials of degree at most n-1, modulo an irreducible polynomial of degree n with 2n input and n output qubits, without ancillary qubits, assuming no errors. With straightforward schoolbook methods this would result in a quadratic number of Toffoli gates and a linear number of CNOT gates. This paper introduces a new algorithm that uses the same space, but by utilizing space-efficient variants of Karatsuba multiplication methods it requires only O(n^{\log_2(3)}) Toffoli gates at the cost of a higher CNOT gate count: theoretically up to O(n^2) but in examples the CNOT gate count looks a lot better.

In this brief, a non-least positive form (NLP) based modular multiplication method that combines Karatsuba and schoolbook multiplication is applied in Montgomery modular multiplication, which saves 2 base multiplications compared to Karatsuba-only designs and allows pipeline structure to make most use of the parallelism in large modular multiplications. Based on this method, 256-bit and 512-bit modular multipliers are constructed with 3-way and 4-way NLP multipliers on FPGA platform. Implemented on Virtex-6, the 256-bit design can perform a modular multiplication in 62.6 ns and only requires 3.5K LUTs and 24 DSPs, which exhibits low-latency and low-cost among previous works.

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

In this paper, we continue the study of bit-parallel multiplier using three-term Karatsuba algorithm (KA), recently introduced by Li et al. (VLSI Design 2018). The three-term KA is the simplest var...

The ${n}$ -term Karatsuba algorithm (KA) is an extension of 2-term KA, which can obtain even fewer multiplications than the original one. The existing ${n}$ -term Karatsuba hybrid $\textit {GF}(2^{m})$ multipliers rely on factorization of ${m}$ or ${m}-1$ , so that put a confinement to these schemes. In this contribution, we use a new decomposition ${m}={n}\ell +{r}$ , such that $0\leq {r} and $0\leq {r} , and propose a novel ${n}$ -term Karatsuba hybrid $\textit {GF}(2^{m})$ multiplier for an arbitrary irreducible trinomial ${x}^{m}+{x}^{k}+1, {m}\geq 2{k}$ . Combined with shifted polynomial basis, a new approach (other than Mastrovito approach) is introduced to exploit the spatial correlations among different subexpressions. We investigate the explicit space and time complexities, and discuss related upper and lower bounds. As a main contribution, the flexibilities of ${n}, \ell $ and ${r}$ make our proposal approaching optimal for any given ${m}$ . The space complexity can achieve to ${m^{2}}/{2}+{O}({\sqrt {11} {m}^{3/2}}/{2})$ , which roughly matches the best result of current hybrid multipliers for special trinomials. Meanwhile, its time complexity is slightly higher than the counterparts, but can be improved for a new class of trinomials. In particular, we demonstrate that the hybrid multiplier for ${x}^{m}+{x}^{k}+1$ , where ${k}$ is approaching $\frac {m}{2}$ , can achieve a better space-time trade-off than any other trinomials.

With the recent advances in quantum computing, code-based cryptography is foreseen to be one of the few mathematical solutions to design quantum resistant public-key cryptosystems. The binary polynomial multiplication dominates the computational time of the primitives in such cryptosystems, thus the design of efficient multipliers is crucial to optimize the performance of post-quantum public-key cryptographic solutions. This manuscript presents a flexible template architecture for the hardware implementation of large binary polynomial multipliers. The architecture combines the iterative application of the Karatsuba algorithm, to minimize the number of required partial products, with the Comba algorithm, used to optimize the schedule of their computations. In particular, the proposed multiplier architecture supports operands in the order of dozens of thousands of bits, and it offers a wide range of performance-resources trade-offs that is made independent from the size of the input operands. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt public-key cryptosystem as representative use cases for large-degree binary polynomial multiplications. For each configuration we showed that our template architecture can deliver a performance-optimized multiplier implementation for each FPGA of the Xilinx Artix-7 mid-range family. The experimental validation performed by implementing our multiplier for all the LEDAcrypt configurations on the Artix-7 12 and 200 FPGAs, i.e., the smallest and the largest devices of the Artix-7 family, demonstrated an average performance gain of 3.6x and 33.3x with respect to an optimized software implementation employing the gf2x C library.

Recently, hybrid multiplication schemes over the binary extension field $GF(2^{m})$ based on $n$ -term Karatsuba algorithm (KA) have been proposed for irreducible trinomials. Their complexities depend on a decomposition of $m$ and the choice of a generation polynomial. However, these multipliers have some limitations on a decomposition of $m$ or generation polynomial $x^{m}+x^{k}+1$ such that $m\geq 2k$ . In this paper, we loosen such limited conditions. We present a new hybrid bit-parallel multiplier based on $n$ -term KA for any irreducible trinomial $x^{m}+x^{k}+1\,\,(0 , where $m$ is decomposed as $m=nm_{0}+r$ with $0 and $1 . (Here, various values for $n,m_{0}$ and $r$ may be chosen.) To this end, we generalize the previously proposed multiplication scheme for $x^{nm_{0}+1}+x^{k}+1$ into $x^{nm_{0}+r}+x^{k}+1$ . We evaluate the explicit complexity of the proposed multiplier. Specific comparisons show that the proposed multiplier achieves the lowest space complexity with the same or lower time complexity among hybrid multipliers. Compared to the fastest multipliers, the time complexity of the proposed multiplier costs only $T_{X}$ higher while its space complexity is much lower (it has roughly 40% reduced space complexity), where $T_{X}$ is the delay of one 2-input XOR gate.

Recently, new multiplication schemes over the binary extension field $GF(2^{m})$ based on an $n$ -term Karatsuba algorithm have been proposed for irreducible trinomials. In this paper, we extend these schemes for trinomials to any irreducible polynomials. We introduce some new types of pentanomials and propose multipliers for those pentanomials utilizing the extended schemes. We evaluate the rigorous space and time complexities of the proposed multipliers, and compare those with similar bit-parallel multipliers for pentanomials. As a main contribution, the best space complexities of our multipliers are $\frac {1}2m^{2}+O\left({m^{\frac {3}2}}\right)$ AND gates and $\frac {1}2m^{2}+O\left({m^{\frac {3}2}}\right)$ XOR gates, which nearly correspond to the best results for trinomials. Also, specific comparisons for three fields $GF(2^{163})$ , $GF(2^{283})$ , and $GF(2^{571})$ recommended by NIST show that the proposed multiplier has roughly 40% reduced space complexity compared to the fastest multipliers, while it costs a few more XOR gate delay. It is noticed that our space complexity gain is much greater than the time complexity loss. Moreover, the proposed multiplier has about 21% reduced space complexity than the best-known space efficient multipliers, while having the same time complexity. The results show that the proposed multipliers are the best space optimized multipliers.

In this paper we introduce a unified field multiplier for the EC kP operation in two different types of Galois fields. The most important contributions of this paper are that the multiplier is based on the 4-segment Karatsuba multiplication method and that it is inherent resistant against selected horizontal attacks., Comment: Author's version accepted for DTIS-2018; the final publication is available at https://ieeexplore.ieee.org/abstract/document/8368560

Modular multiplication of very long integers is a key building block of fully homomorphic encryption and elliptic curve cryptography. The Karatsuba algorithm reduces the multiplication complexity by decomposing the operands into shorter segments. However, in the case of long numbers, adding up the segment products to derive the final product and then carrying out modular reduction as in previous designs can take many clock cycles. This paper focuses on moduli in the format of Solinas prime and proposes to integrate modular reduction into every segment product of the Karatsuba integer multiplication. As a result, the length of the intermediate results is further reduced and they can be added up simultaneously by using a carry-save adder at the cost of small area increase. Additionally, the computation scheduling are optimized to reduce the required number of registers and multiplexers. Complexity analysis shows that, for decomposition factors of 2, 3 and 4, our design requires on average 18.5% less clock cycles with only 5.9% area overhead and similar critical path compared to carrying out the modular reduction on the final product.

Internet of Things (IoT) consists of various physical devices over the internet to communicate and exchange data with other devices and systems. By and large, IoT is dominated by resource constrained handheld devices. The major challenge to these devices is providing physical device security and network security. Elliptic Curve Cryptography (ECC) is an optimal solution for providing security in key exchange and digital signature. It requires very less memory, can perform faster field operations, and provides better resistance to side-channel-attacks, compared to other cryptography mechanisms. In this paper, we propose two different architectures- high-performance and lightweight. Both designs are hardware implementation of ECC over Curve25519, based on Montgomery ladder multiplication. Our high-performance architecture uses a modular hybrid adder and two stage pipelined Karatsuba multiplier. The lightweight architecture consists of Karatsuba multiplier and Brent Kung adder. We have designed a Physically Unclonable Function (PUF) to generate a true random number which is utilized to produce non-deterministic output from the design. An optimized LZ77 software CODEC is developed to achieve higher unicity-distance and throughput. Both designs are implemented on Xilinx Zynq 7000 FPGA. The result shows that our high-performance architecture can execute variable-base scalar point multiplication operation in 20201 cycles at 192 MHz frequency. The proposed architecture achieved 26.57% improvement in execution time than previous work. The lightweight design needs 693771 clock cycles, occupies 443 slices to perform one point multiplication. Our lightweight architecture reduces execution time and DSP_countXTime by 50.4% compared to recent implementations. Finally, various techniques are embedded in the proposed designs to countermeasure various side-channel attacks.

The IoT structures use data as a general rule; the data arrangement from contraptions can moreover be a goal of cyberattacks. It is a direct result of this that countermeasures dependent on encryption are as of now picking up in significance. Trivial (lightweight) cryptosystem is an encryption approach which includes slight impress with low-computational multifaceted nature. A few difficulties can block the fruitful execution of an IoT framework and its associated gadgets, including security, interoperability, power/handling capacities, adaptability, and accessibility. Many of these can be addressed with IoT gadget the board, for example, by accepting standard IoT conventions like lightweight M2M or utilising a comprehensive IoT gadget the executives stage offered by a reliable supplier as part of a SaaS model. In this paper, we propose a simple cryptography protocol for securing resource-constrained devices that uses Optimised ECC with Karatsuba algorithm (OECC-KA) for fast multiplication. Several efficient cryptographic algorithms have been widely used for resource constraint device; it may not be suitable with its limited computing power, bandwidth and CPU power. Elliptic curve cryptography is the best choice for limited power usage with high-level security. The traditional elliptic curve cryptography occupies 80% of execution time for scalar multiplication. The proposed optimized ECC with Karatsuba algorithm increases the execution time with fast multiplication algorithm.

This paper mainly described about design and synthesis of 16-bit Karatsuba multiplier using Square root carry select adder (SRCSA) circuit. The Carry look ahead adder (CLA), Carry save adder (CSA) and SRCSA are modelled using Verilog HDL. The functional verification of all the adders is carried out in Cadence NClaunch tool. All the adders are synthesized in Cadence Genus tool. The power, timings and area reports can be generated in the synthesis flow. The comparative analysis done between CLA, CSA and SRCSA. Later choose SRCSA for the multiplier. The Karatsuba multiplier is designed using the Verilog HDL. The functional verification of the multiplier circuit is carried using Verilog (RTL file) and test bench in NCLaunch tool from cadence. The synthesis of multiplier circuit is carried in Genus tool from Cadence, it converts the RTL file to gate-level netlist. During synthesis, reported the power is 193385.696 nW, Delay is 3409ps and area is 2795.508nm2. All process has been carried out using the 180nm technology.