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The Internet of Things (IoT) has witnessed a significant surge in adoption, particularly through the utilization of Wireless Sensor Networks (WSNs), which comprise small internet-connected devices. These deployments span various environments and offer a multitude of benefits. However, the widespread use of battery-powered devices introduces challenges due to their limited hardware resources and communication capabilities. In response to this, the Internet Engineering Task Force (IETF) has developed the IPv6 Routing Protocol for Low-power and Lossy Networks (RPL) to address the unique requirements of such networks. Recognizing the critical role of RPL in maintaining high performance, this paper proposes a novel approach to optimizing power consumption. Specifically, it introduces a developed sensor motes topology integrated with a Radio Duty Cycling (RDC) mechanism aimed at minimizing power usage. Through rigorous analysis, the paper evaluates the power efficiency of this approach through several simulations conducted across different network topologies, including random, linear, tree, and elliptical topologies. Additionally, three distinct RDC mechanisms--CXMAC, ContikiMAC, and NullRDC--are investigated to assess their impact on power consumption. The findings of the study, based on a comprehensive and deep analysis of the simulated results, highlight the efficiency of ContikiMAC in power conservation. This research contributes valuable insights into enhancing the energy efficiency of RPL-based IoT networks, ultimately facilitating their widespread deployment and usability in diverse environments. [ABSTRACT FROM AUTHOR]

The RPL (IPv6 Routing Protocol for Low-Power and Lossy Networks) protocol is essential for efficient communication within the Internet of Things (IoT) ecosystem.Despite its significance, RPL's susceptibility to attacks remains a concern. This paper presents a comprehensive simulation-based analysis of the RPL protocol's vulnerability to the decreased rank attack in both static and mobile network environments.We employ the RandomDirectionMobility Model (RDM) for mobile scenarios within the Cooja simulator. Our systematic evaluation focuses on critical performance metrics, including Packet Delivery Ratio (PDR), Average End to End Delay (AE2ED), throughput, Expected Transmission Count (ETX), and Average Power Consumption (APC). Our findings illuminate the disruptive impact of this attack on the routing hierarchy, resulting in decreased PDR and throughput, increased AE2ED, ETX, and APC. These results underscore the urgent need for robust security measures to protect RPLbased IoT networks. Furthermore, our study emphasizes the exacerbated impact of the attack in mobile scenarios, highlighting the evolving security requirements of IoT networks. [ABSTRACT FROM AUTHOR]

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%. [ABSTRACT FROM AUTHOR]

This paper presents a concurrent error correcting adder design employing fault tolerance through a duplication of a bit slice of a full adder based on alternative computation. The duplicated module is based on computing the sum and carry bits in two alternative ways so that faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. Redundancy is used to provide fail-operational functionality. If one hardware component goes down, then one of the redundant components can be brought in to continue operation of the system. The proposed method is simulated in standard CMOS 32nm technology and provides 11.11% saving in transistor count compared to a QMR (Quadruple Modular Redundancy) style design. [ABSTRACT FROM AUTHOR]