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Electron-beam writer characterization is key to enable predictable product performance in a photomask shop. This is traditionally done by writing test patterns with one distinct tool on one blank. Within this article, we introduce a method that reduces uncertainty caused by variation of blanks and process parameters, by using multiple, subsequent electronbeam exposure steps with different same-of-a-kind tools. The method is demonstrated for the disentanglement of two of the most fundamental parameters in an e-beam tool, current density and blanker latency, which together determine the actual dose. Additional accuracy can be achieved by probing the same tool parameter with different methods, which is shown by comparing Critical Dimension Scanning Electron Microscopy of line-space patterns below the maximum shot size with Thin Film Optical Scatterometry of comparatively large pads. The multiple exposure method needs a proper correction of systematic effects caused by contact of exposed areas with air during mask transfer from one writer to another, which are presented and discussed.

In this paper, the feasibility of a large area exposure for the manufacturing of a NIL master (silicon wafer) dealing with a long writing time is shown. Fraunhofer CNT succeeded in a 355h exposure with a variable shaped e-beam using a commercially available positive tone chemically amplified resist. The wafer has been evaluated in terms of resist contrast and stability, CD uniformity, linearity, pattern quality and defectivity. Electron beam tool parameters like Wehnelt voltage and stage temperature have been analyzed. Different writing strategies and concepts will be considered to optimize the exposure and minimize stitching error defects.

Electron optics can assist in the fabrication of semiconductor devices in many challenges that arise from the ongoing decrease of structure size. Examples are augmenting optical lithography by electron beam direct write strategies and high-throughput imaging of patterned structures with multiple beam electron microscopes. We use multiple beam electron microscopy to image semiconductor wafers processed by electron beam lithography.

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50nm.

Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

This paper focuses on the scaling and optimization of metal-isolator-metal capacitors integrated in 3D Si structures. Scaling to high capacitance density is aimed by the use of high-k dielectrics and a significant area enhancement realized through silicon pattering with increasing aspect ratios. By material and process optimization the capacitors show excellent IV and CV characteristics with high temperature and reliability performance independently of the 3D structure. A fully functional capacitor of 4mm2 consisting of 80 Mil trenches with an overall capacitance of 850nF can be demonstrated.

This paper focuses on zirconia and TiN based metal-isolator-metal capacitors integrated in immediate vicinity to the Si substrate. A high capacitance density is aimed by significant area enhancement realized through silicon pattering. By material optimization the capacitors also withstand higher supply voltages and show excellent temperature and reliability performance independently of the 3D structure.

Resist processing for future technology nodes becomes more and more complex. The resist film thickness is getting thinner and hardmask concepts (trilayer) are needed for reproducible etch transfer into the stack. Additional layers between resist and substrate are influencing the electron scattering in e-beam lithography and may also improve sensitivity and resolution. In this study, bare silicon wafers with different assisting underlayers were processed in a 300 mm CMOS manufacturing environment and were exposed on a 50 keV VISTEC SB3050DW variable-shaped electron beam direct writer at Fraunhofer CNT. The underlayers are organic-inorganic hybrid coatings with different metal additives. The negative-tone resist was evaluated in terms of contrast, sensitivity, resolution and LWR/LER as a function of the stack. The interactions between resist and different assisting underlayers on e-beam direct writing will be investigated. These layers could be used to optimize the trade-off among resolution, LWR and sensitivity in future applications.

While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct patterning is still being considered as an alternative or complementary approach for patterning of advanced technology nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore, degradation of product reliability may occur. These questions have not yet been clarified in detail. For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits, suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.