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A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.

The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative high-performance low-energy solutions to the programming problem using techniques such as reconfiguration to construct optimized architectures for a given computational problem. Exploiting the opportunities offered by these architectural innovations obviously requires a clear understanding of the trade-off's offered by the various architectural models and styles, as well as a well-thought out design methodology, combining high-level prediction and analysis tools with partitioning, optimization and mapping techniques. This paper presents an overview of opportunities of these reconfigurable architectures in the architecture domain.

In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited by the hard-wired macros to be incorporated such as DCT and Quantizer. A microprocessor or a media-processor with multimedia-enhanced instructions has not yet been applied to MPEG2 encoding. This DSP for real-time codec applications has the following features: (a) extensive use of data parallelism inside the macro-block data structure, (b) flexible data path for coding algorithms to enhance gate utilization and to reduce the use of macro-block pipeline memory, (c) data path design suitable for (but not limited to) fast DCT/IDCT algorithms.

We developed a soft macro cell generator which generates discrete cosine transform (DCT) macro cells for various video compression requirements. Because of the proposed fast algorithm, hardware implementation, and customized flip flop cells, a generated macro cell is as small as any other full custom DCT LSI and macro cell, although the generator's output is a soft macro cell. Furthermore an equivalent C language model and an accuracy report necessary for parameter optimization of complex DCT arithmetic are also generated. An MPEG-quality DCT macro cell has been generated and fabricated on 0.7 /spl mu/m 3-metal CMOS for performance evaluation, such as cell speed, size, and design time.