36 results on '"Kazeminia, Sarang"'
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2. A low-jitter leakage-free digitally calibrated phase locked loop
3. A 17 MS/s SAR ADC with energy-efficient switching strategy
4. Dual-path linearization technique for bandwidth enhancement in SAH circuits
5. A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs
6. A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs
7. A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability
8. Robust sliding-mode control for maximum power point tracking of photovoltaic power systems with quantized input signal
9. Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy
10. An extendable global clock high-speed binary counter compatible to the FPGA CLBs
11. Programmable incrementing/decrementing binary accumulator for high-speed calibration loops
12. Modelling of Friction Stir Extrusion using Artificial Neural Network (ANN).
13. Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch
14. Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs
15. Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs
16. Bulk controlled offset cancellation mechanism for single-stage latched comparator
17. A 800MS/s, 150µV input-referred offset single-stage latched comparator
18. Dual-loop enhanced-gain fast-response CMFB for open-loop RAs in high-resolution ADCs
19. A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop
20. A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs
21. A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump
22. A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs
23. Producing flat supply voltage using a temperature-compensated BGR within LDO regulator loop
24. Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump
25. A 250MHz to 4GHz adaptive bias tuned PLL for low-jitter applications based on a fast response VCO oscillating cells
26. On the stability of integer-N phase locked loops based on a straightforward design methodology
27. Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy
28. A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop.
29. Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs
30. A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector
31. Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage
32. A 500 MS/s 600 .MU.W 300 .MU.m2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 .MU.m 3.3 v CMOS Process
33. High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection
34. On matching properties of R-2R ladders in high performance digital-to-analog converters
35. An 8-bit 2.5GS/s D/A converter in 0.35µ CMOS technology with improved pipeline structure
36. A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump.
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