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This paper presents a load-adaptive Class-G headphone amplifier to improve the power efficiency for different headphone impedances. For an impedance value, the amplifier utilizes two techniques, voltage rails selection and Class-G switching activity control, to reduce the power dissipation of the amplifier and the power loss of a Class-G power generator, respectively. In addition, a supply-rejection bandwidth enhancement technique for the Class-AB output stage is proposed to suppress the out-of-band noise by the Class-G supply rails switching. Compared with the conventional fixed 2-level Class-G amplifier, the integrated $0.18~\mu \text {m}$ CMOS amplifier improves the total-path efficiency to 37% from 31% (1.45 mA current can be saved from a 1.8 V supply) while delivering 5 mW into a $16~\Omega $ . The PSRR of the amplifier is 130 dB at 217 Hz and is still larger than 100 dB up to 20 kHz. Finally, the decoder and amplifier together achieve 108 dB DR and 95 dB SNDR with a $16~\Omega $ headphone load.

A Class-G headphone amplifier for hi-fi audio playback with high immunity to supply disturbance and Class-G switching noise is presented that achieves 130dB PSRR at 217Hz and higher than 100dB PSRR up to 20kHz. In addition, a Class-G amplifier with load-adaptive voltage supply rails selection and Class-G switching scheme improves the power efficiency for different impedances. Realized in 0.18μm CMOS, the decoder and amplifier together achieve 108dB DR and 95dB SNDR with a 16D headphone load.

As the data rate increases above Gb/s, the design of a clock and data recovery (CDR) circuit becomes a great challenge. A 3.125-Gb/s CDR is proposed to shorten the frequency acquisition time by employing a wide-linear-range frequency detector. Fabricated in a 0.18-mum 1P6M CMOS technology, the output jitter of this proposed CDR is measured as 70 ps (peak-to-peak) and 8.3 ps (rms). The measured bit-error rate (BER) is less than 10-12 for 231-1 PRBS. The proposed CDR occupies a chip area of 0.61 mm times 0.61 mm and dissipates 61 mW from a single 1.8-V power supply.

A low-jitter distributed DLL for multiple-phase clock generation is proposed. The distributed DLL monitors the phase difference for each output clock and the reference clock. This distributed DLL is fabricated in a 90 nm CMOS process and consumes 15 mW from a 1 V supply excluding output buffers. The distributed DLL operates from 8 to 10 GHz, which is consistent with the simulation results and also the fastest in CMOS technology.

A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.

A distributed-load static frequency divider is designed in a 0.13-mum CMOS technology for wideband operation. The technique of a distributed load utilized in a current-mode logic (CML) circuit improves operating frequency by about 30% based on simulation results. Driven by a differential signal, the divider operates from 16 to 40 GHz while consuming 10 mW from a 2-V power supply

A delay-locked loop (DLL)-based frequency multiplier is designed for the ultrawideband (UWB) mode-1 system. This clock generator with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The UWB clock generator has been fabricated in a 0.18-/spl mu/m CMOS process and consumes only 54 mW from a 1.8-V supply while exhibiting a sideband magnitude of -35.3 dB and -94 dBc/Hz phase noise at the frequency offset of 50 kHz.