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Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge

The permeability of mesh wicks is important for various applications, for example two-phase heat transfer. However, our understanding of the permeability of single-layer, free-standing mesh wicks (SLFSMW), with liquid-gas interfaces on both sides, is limited. We present a novel and simpler method to determine the permeability of a SLFSMW and apply it to a representative mesh. Our method involves modifying the capillary pressures elevation and simultaneously measuring the permeability to determine the permeability-capillary pressure relationship. When applied to a copper mesh with plain weave having undergone careful surface cleaning, the permeability is found to decrease as capillary pressure for deionized (DI) water increases. We present dimensional analysis to generalize our data for other mesh sizes with similar weaves, and fluids. We model the behavior of mesh in application based on the integration of Darcy’s law with an analytic function fit to measured data and conduct parametric studies to investigate the superficial velocity of liquids through the mesh under varying driving pressures, transport lengths, and liquid viscosity based on the obtained capillary pressure-permeability relationship. This study provides valuable insights into the transport properties of mesh wicks, with potential applications in fields such as electronics cooling, electrochemical devices, and fluid purification technologies.

The thermal conductivities of doped polysilicon layers depend on grain size and on the concentration and type of dopant atoms. Previous studies showed that layer processing conditions strongly influence the thermal conductivity, but the effects of grain size and dopant concentration were not investigated in detail. The current study provides thermal conductivity measurements for low-pressure chemical-vapor deposition (LPCVD) polysilicon layers of thickness near 1 /spl mu/m doped with boron and phosphorus at concentrations between 2.0/spl times/10/sup 18/ cm/sup -3/ and 4.1/spl times/10/sup 19/ cm/sup -3/ for temperatures from 20 K to 320 K. The data show strongly reduced thermal conductivity values at all temperatures compared to similarly doped single-crystal silicon layers, which indicates that grain boundary scattering dominates the thermal resistance. A thermal conductivity model based on the Boltzmann transport equation reveals that phonon transmission through the grains is high, which accounts for the large phonon mean free paths at low temperatures. Algebraic expressions relating thermal conductivity to grain size and dopant concentration are provided for room temperature. The present results are important for the design of MEMS devices in which heat transfer in polysilicon is important.

Metal-oxide thermal boundary conductance (TBC) strongly influences the temperature rise in nanostructured systems, such as dense interconnects, when its value is comparable to the thermal conductance of the amorphous dielectric oxide. However, the thermal characterization of metal-amorphous oxide TBC is often hampered by the measurement insensitivity of techniques such as time-domain thermoreflectance (TDTR). Here, we use metal nanograting structures as opto-thermal transducers in TDTR to measure the TBC of metal-oxide interfaces. Combined with an ultrafast pump-probe laser measurement approach, the nanopatterned structures amplify the contribution of the thermal boundary resistance (TBR), the inverse of TBC, over the thermal resistance of the adjacent material, thereby enhancing measurement sensitivity. For demonstration purposes, we report the TBC between Al and SiO2 films. We then compare the impact of Al grating dimensions on the measured TBC values, sensitivities, and uncertainties. The grating periods L used in this study range from 150 to 300 nm, and the bridge widths w range from 72 to 205 nm. With the narrowest grating transducers (72 nm), the TBC of Al-SiO2 interfaces is measured to be 159-48+61 MW m-2 K-1, with the experimental sensitivity being 5× higher than that of a blanket Al film. This improvement is attributed to the reduced contribution of the SiO2 film thermal resistance to the temperature signal from TDTR response. The nanograting measurement approach described here is promising for the thermal characterization of a variety of nanostructured metal-amorphous passivation systems and interfaces common in semiconductor technology.

The Intrachip Enhanced Cooling Fundamentals (ICECool Fun) effort was launched by the Defense Advanced Research Projects Agency (DARPA) under the leadership of Dr. Avram Bar-Cohen during 2012–2015 to target an order of magnitude improvement in chip level and hot spot heat fluxes, compared to the then state-of-the-art (SOA). Evaporative cooling technologies to achieve potential targets of 1 kW/cm2 at the chip level and 5 kW/cm2 at the hot spot level were targeted. A key goal was to improve fundamental understanding of the evaporative cooling physics at the relevant scales, and a numerical modeling capability to enable the co-design of such solutions in emerging computing and communications systems. A summary of the five projects pursued under this effort is provided, including the key accomplishments and developed capabilities.

Superlattice-like phase change memory (SL-PCM) promises lower switching current than conventional PCM based on Ge2Sb2Te5 (GST); however, a fundamental understanding of SL-PCM requires detailed characterization of the interfaces within such an SL. Here we explore the electrical and thermal transport of SLs with deposited Sb2Te3 and GeTe alternating layers of various thicknesses. We find up to an approximately four-fold reduction of the effective cross-plane thermal conductivity of the SL stack (as-deposited polycrystalline) compared with polycrystalline GST (as-deposited amorphous and later annealed) due to the thermal interface resistances within the SL. Thermal measurements with varying periods of our SLs show a signature of phonon coherence with a transition from wave-like to particle-like phonon transport, further described by our modeling. Electrical resistivity measurements of such SLs reveal strong anisotropy (∼2000×) between the in-plane and cross-plane directions due to the weakly interacting van der Waals-like gaps. This work uncovers electrothermal transport in SLs based on Sb2Te3 and GeTe for the improved design of low-power PCM.

Interfaces govern thermal transport in a variety of nanostructured systems such as FinFETs, interconnects, and vias. Thermal boundary resistances, however, critically depend on the choice of materials, nanomanufacturing processes and conditions, and the planarity of interfaces. In this work, we study the interfacial thermal transport between a nonreactive metal (Pt) and a dielectric by engineering two differing bonding characters: (i) the mechanical adhesion/van der Waals bonding offered by the physical vapor deposition (PVD) and (ii) the chemical bonding generated by plasma-enhanced atomic layer deposition (PEALD). We introduce 40-cycle (∼2 nm thick), nearly continuous PEALD Pt films between 98 nm PVD Pt and dielectric materials (8.0 nm TiO2/Si and 11.0 nm Al2O3/Si) treated with either O2 or O2 + H2 plasma to modulate their bonding strengths. By correlating the treatments through thermal transport measurements using time-domain thermoreflectance (TDTR), we find that the thermal boundary resistances are consistently reduced with the same increased treatment complexity that has been demonstrated in the literature to enhance mechanical adhesion. For samples on TiO2 (Al2O3), reductions in thermal resistance are at least 4% (10%) compared to those with no PEALD Pt at all, but could be as large as 34% (42%) given measurement uncertainties that could be improved with thinner nucleation layers. We suspect the O2 plasma generates stronger covalent bonds to the substrate, while the H2 plasma strips the PEALD Pt of contaminants such as carbon that gives rise to a less thermally resistive heat conduction pathway.

Mesoporous metals are used in applications requiring high specific surface area and fast mass transport in an electrically conductive network and are primarily produced via dealloying. However, dea...

Thermal regulators and switches are nonlinear devices that can greatly aid in the management of transient and/or spatially varying heating events. Various physical mechanisms have been harnessed to achieve nonlinear and switchable thermal behavior, though device characteristics are often evaluated in terms of steady-state performance only. Accurately capturing the transient behavior of these devices is a crucial missing link required for assessing the effectiveness of implementation in real-world scenarios. Here, we explore the physics of binary vapor diffusion through a noncondensable gas cavity as a promising mechanism for high-resistance contrast thermal regulation. Through a parametric steady-state optimization, we present a roadmap for future designs that can potentially reach switching ratios of up to 14.5. In addition, we perform a transient investigation to characterize the thermal response time of the device. The device possesses an extremely desirable attribute under certain transient heat loads, where the effective switching ratio appears significantly greater than the steady-state ratio due to a temporary increase in the OFF-state resistance immediately after switching. This work informs future experimental efforts for design optimization of binary-diffusion-based regulators and establishes simple modeling schemes to approximate device performance in system-level regulation scenarios.

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density ( ${J} _{\text{reset}}$ ) and power ( ${P} _{\text{reset}}$ ) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications.

This article presents GaN two-dimensional electron gas (2DEG) Hall plates with low residual offset and noise at 3 V input bias. We studied devices made from three consecutive fabrication generations through current spinning offset measurements in a zero-field chamber. When operated above 1 V, the first-generation devices charted high residual offsets >1 mT. We reduced these residual offsets by three orders of magnitude in later device generations. Two experiments were performed to confirm the improvements. First, the GaN 2DEG Hall-effect plates were measured with infrared microscopy during current spinning to investigate current crowding and Joule heating. The low offset devices had minimal thermal gradients while the high offset devices had large thermal variations during current spinning. Second, zero-field current spinning was used to compare GaN 2DEG Hall-effect plates against typical commercial silicon Hall-effect plates. The Si devices had residual offsets $> 10\mu \text{T}$ biased at 3 V and AlGaN/GaN devices had residual offset $ at 3 V, and an InAlN/GaN devices operated at 2 V had a residual offset $ . Thus, for the first time, GaN 2DEG Hall-effect plates were shown to operate with high bias with low offsets and noise, which enables high fidelity sensing applications in extreme environments. [2020–0176]

Designing materials with ultralow thermal conductivity has broad technological impact, from thermal protection to energy harvesting. Low thermal conductivity is commonly observed in anharmonic and strongly disordered materials, yet a microscopic understanding of the correlation to atomic motion is often lacking. Here we report that molecular insertion into an existing two-dimensional layered lattice structure creates a hybrid superlattice with extremely low thermal conductivity. Vibrational characterization and

Layering two-dimensional van der Waals materials provides a high degree of control over atomic placement, which could enable tailoring of vibrational spectra and heat flow at the sub-nanometer scale. Here, using spatially resolved ultrafast thermoreflectance and spectroscopy, we uncover the design rules governing cross-plane heat transport in superlattices assembled from monolayers of graphene (G) and MoS

Phase change thermal management devices including heat pipes and ultra-thin vapor chambers can remove and spread the excess heat from microprocessors more efficiently compared with the conventional heat sinks. However, the capillary and CHF limits of the evaporator section remained a challenge for high heat flux (> 100 Wcm−2) large area (> 5 × 5 mm2) applications. In this study, a hybrid microporous structure consists of copper wire meshes (CWMs) as the liquid delivery routing and copper inverse opals (CIOs) film as the boiling/evaporation platform is proposed. The feasibility of the approach and the design optimization were studied with extensive modeling and CFD simulations. For the experiment setup, the heater and the RTD sensors are fabricated over a Silicon chip using the conventional micro fabrication processes and the micro porous copper film is deposited based on template-assisted electrodeposition, resulting in CIOs structure with average 5 μm pore size, 1 μm neck, and 15 μm thickness. A copper wire mesh structure (500 μm thickness, 0.5 porosity, 71 μm wire diameter) with 4 × 4 tile openings (1 × 1 mm2 area per tile) was fixed over the CIOs film with mechanical constraints. A flow loop and vapor chamber are designed and fabricated to perform capillary boiling experiments in a saturated environment (liquid water and vapor at ∼100°C). The hybrid microporous structure was able to remove over 75 W from the 5 × 5 mm2 heater area (over 300 W cm−2 heat flux) with 9°C super heat resulting in thermal resistance of 0.03 cm2°CW−1 at the CHF. The findings of this study are largely beneficial for the design and fabrication of high performance evaporator wicks and next-generation heat routing technologies.

Two-phase, capillary-fed cooling devices are appealing thermal management technologies due to their potential for high heat transfer performance and ease of system-level integration. While existing evaporative wicking structures such as copper inverse opals (CIOs) and copper wire meshes (CWMs) have shown promise for achieving target heat dissipation rates of 100 Wcm−2 or greater, the reliability of these structures for long-term device operation and optimal capillary-driven boiling performance has not received much attention. To ensure proper functionality of the evaporator wick, the microporous copper structures must retain a hydrophilic contact angle during device operation. Surface oxidation of the copper is a critical degradation mechanism that must be addressed to preserve the integrity of the wick. In this study, we systematically investigate the contact angle change of untreated copper and various copper oxides under different conditions. To avoid the formation of hydrophobic Cu2O, we pre-oxidize the copper micro porous wick to form hydrophilic cupric oxide CuO and study the effect of various thermal and chemical oxidation recipes on the hydrophilicity and morphology of the resulting structures. A chemical oxidation formula is implemented for the creation of a stable superhydrophilic surface at a low temperature (70°C) for copper inverse opals (CIOs) (5 μm pore size) and copper wire meshes (CWMs) (76 μm pore opening). The recipe has been optimized to create nano CuO needles with a length of < 100 nm and keep the necks (∼1 μm diameter) open for better capillary wicking of the working fluid. The findings of this study potentially benefit the development of copper-based capillary-fed cooling devices.

We propose and demonstrate a two-dimensional 4-bit fully optical nonvolatile memory using Ge2Sb2Te5 (GST) phase change materials, with encoding via a 1550 nm laser. Using the telecom-band laser, we...

Aggressive thermal management strategies such as liquid cooling have become essential for high-performance three-dimensional (3D) integrated circuit (IC) chips. Micro-pin fin arrays integrated between stacks can provide superior thermal performance with relatively less pumping power compared to microchannel cooling. In this work, we experimentally studied the single-phase heat transfer and pressure drop characteristics of micro-pin fin arrays. Three different samples consisting of 31–131 rows of cylindrical micro-pin fins with pin diameters D h = 45–100 μm, center-to-center pin spacings S = 74–298 μm, and pin height H f ∼ 200 μm were tested. Dielectric fluid R245fa was used as the working fluid with mass flow rates m = 14.7–181.6 g/min and corresponding Reynolds numbers Re = 35–481.3. The heat fluxes ranged from 2.5 W/cm 2 to 48.7 W/cm 2 , and the inlet fluid temperature was maintained at ambient temperature in the range of 22.2–25.3 °C. The local heater temperature distributions, average heat transfer characteristics, and pressure drops for various geometries of the embedded microfluid pin–fin arrays were determined. The experimentally determined heat transfer coefficient varied with both the mass flow rate and pin spacing with an averaged heat transfer coefficient of up to 18.2 kW/(m 2 ·K). Full-scale conjugate simulations with a turbulence model were conducted using ANSYS Fluent to validate the experimental results for the three cases. A comparison with the numerical model showed mean absolute errors of 9.1% for the heat transfer and 14.3% for the pressure drop.

This paper demonstrates a post-fabrication technique for creating highly compliant structures inside a hermetic, wafer-scale encapsulation process. Single crystal silicon micro-tethers were fabricated alongside compliant structures to temporarily provide additional anchoring and increased device rigidity during the fabrication process. This technique mitigates in-process stiction for compliant devices by tethering the large, free-moving structures during fabrication. After successful fabrication, the micro-tethers can be selectively removed by two methods. The first method utilizes a potential voltage difference across the device. Joule heating can be concentrated in the micro-tether and the device separated after supplying requisite heat energy. The second method utilizes mechanical fracturing where a large external force is applied to separate the device from the tether. Micro-tethers in this paper were attached to differential resonant beam accelerometers, and were designed for detachment by each method: Joule heating and mechanical fracture. Our results show that the $40\mu \text{m}$ thick device can be successfully detached by both methods, indicated by the device sensitivity increase from ~100 Hz/g to ~400 Hz/g. [2018-0091]

The thermal deformation of silicon-based X-ray and high-power laser optics is a strong function of the beam power and footprint, mirror geometry as well as the location of the “convective” thermal management solution. Previous research carefully optimized the impact of these parameters and arrived at the “Topside cooling” design concept (smart-cut notches) that reduced the thermal slope error (sub-μrads) by 3-5 orders of magnitude compared to the baseline mirror bottom-side cooling [1,2]. The present work introduces internal embedded microchannel cooling which brings the cooling solution to the close proximity of the laser beam footprint and also reduce thermal spreading. The thermomechanical finite element modelling (FEM) results show that embedded microchannel cooling can reduce the thermal deformation in RMS-Uy by a factor of 40 and 13 compared with topside cooling, for Gaussian distribution beam heat flux with full width half maximum (FWHM) 20 mm and 40 mm, respectively.

Superlattice-like phase change memory (SL-PCM) promises lower switching current than conventional PCM based on Ge

Capillary-fed boiling in microporous copper inverse opals (CIOs) is capable of removing an excess of 1 kW/cm2 at 10–15 °C superheat over small wicking distances ∼ 200 μm. In order to remove heat from large area chips (> 1 cm2), longer capillary wicking distance is desired to reduce the manufacturing complexity of the 3D manifold for liquid delivery and vapor extraction. In this study, we propose graded copper inverse opals (g-CIOs) where smaller pores at the bottom provide high capillary pressure for liquid delivery, while larger pores at the top reduce viscous pressure drop for vapor extraction. This nonhomogeneous wicking material decouples the permeability and capillary pressure in the vertical and lateral directions, resulting in greater CHFs and capillary wicking distances. In this study, we demonstrate the feasibility of fabricating g-CIOs material with up to three different pore diameters (2 μm, 5 μm, and 10 μm) using a multi-step template sintering and copper electrodeposition process. We then leverage and expand upon a well-calibrated experimental model for the prediction of CHF in monoporous CIOs to map the performance metrics for g-CIOs. The model combines a hydraulic resistance network with Darcy’s law and accounts for the nonhomogeneous permeabilities in lateral and vertical directions. Using this model, we study the impact of total wick thickness and graded pore-size combinations on the critical heat fluxes and wicking distances. Our modeling results conclude that a two-layer g-CIOs can potentially reach ∼70% enhancement in the critical heat flux or ∼30% enhancement in the wicking length compared to monoporous CIOs of the same thickness. Our fabrication capability and preliminary modeling results offer the opportunity to design boiling tests with optimized g-CIOs and exploring the potential of dissipating high heat flux for large area cooling applications.

This paper reviews recent progress in the development of silicon-based vapor chambers for heat spreading in electronic packages. Effective hotspot mitigation is an increasingly challenging issue in electronics thermal management, and the use of silicon vapor chambers creates opportunities for thermal-expansion matched, high performance heat spreaders that can be directly integrated with the semiconductor die. While silicon microheat pipes have been extensively studied as one-dimensional heat transport mechanisms for heat routing in semiconductor substrates, silicon vapor chambers require special consideration and different manufacturing approaches due to the different heat transport configurations involved. The following review therefore provides an overview on the evolution of silicon vapor chambers in terms of fabrication strategies and performance characterization. Particular focus is given to opportunities and challenges associated with using silicon as the vapor chamber envelope material rather than more traditional metal-based vapor chambers, such as the ability to optimize the wick geometry with greater fidelity and issues with manufacturing scalability.

Layering two-dimensional van der Waals materials provides unprecedented control over atomic placement, which could enable tailoring of vibrational spectra and heat flow at the sub-nanometer scale. Here, using spatially-resolved ultrafast thermoreflectance and spectroscopy, we uncover the design rules governing cross-plane heat transport in superlattices assembled from monolayers of graphene (G) and MoS2 (M). Using a combinatorial experimental approach, we probe nine different stacking sequences: G, GG, MG, GGG, GMG, GGMG, GMGG, GMMG, GMGMG and identify the effects of vibrational mismatch, interlayer adhesion, and junction asymmetry on thermal transport. Pure G sequences display signatures of quasi-ballistic transport, whereas adding even a single M layer strongly disrupts heat conduction. The experimental data are described well by molecular dynamics simulations which include thermal expansion, accounting for the effect of finite temperature on the interlayer spacing. The simulations show that a change of only 1.5% in the layer separation can lead to a nearly 100% increase of the thermal resistance. Using these design rules, we experimentally demonstrate a 5-layer GMGMG superlattice with an ultralow effective cross-plane thermal conductivity comparable to air, paving the way for a new class of thermal metamaterials with extreme properties.

Layered two-dimensional (2D) materials such as MoS

Transmission electron microscopy (TEM) is arguably the most important tool for atomic‐scale material characterization. A significant portion of the energy of transmitted electrons is transferred to the material under study through inelastic scattering, causing inadvertent damage via ionization, radiolysis, and heating. In particular, heat generation complicates TEM observations as the local temperature can affect material properties. Here, the heat generation due to electron irradiation is quantified using both top‐down and bottom‐up approaches: direct temperature measurements using nanowatt calorimeters as well as the quantification of energy loss due to inelastic scattering events using electron energy loss spectroscopy. Combining both techniques, a microscopic model is developed for beam‐induced heating and to identify the primary electron‐to‐heat conversion mechanism to be associated with valence electrons. Building on these results, the model provides guidelines to estimate temperature rise for general materials with reasonable accuracy. This study extends the ability to quantify thermal impact on materials down to the atomic scale., Electron beam is converted to heat via inelastic scattering while traversing a solid‐state medium and the generated heat often complicates experimental analysis. A nanocalorimeter enables capturing heat generation induced by electron beams, and in parallel, the electron energy loss spectroscopy measurements reveal that a key energy conversion is to be responsible for the electrons in an outer shell.