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A ferroelectric-gated nanoelectromechanical (NEM) nonvolatile random-access memory cell [negative capacitance (NC)-NEM memory] is proposed and investigated. By adjusting the structural parameters of the NEM relay, the pull-in voltage of the NC-NEM memory cell can be reduced, and its pull-out voltage can even become negative. Hence, an NEM relay with a ferroelectric layer in the gate stack can be used as a nonvolatile random-access memory cell. Herein, the device design and operational principles for read/program/erase are introduced in detail. The program/erase voltage and the program delay time of the NC-NEM memory cell have been quantitatively estimated.

The operating voltage of a nanoelectromechanical (NEM) relay can be scaled down significantly using negative capacitance (NC), which is a unique property of ferroelectric materials. It has been observed that a ferroelectric capacitor can amplify the internal voltage of a device (higher than the externally applied voltage) by means of the NC effect. In this simulation work, depending on the structural parameters of a ferroelectric capacitor and an NEM relay, an NC + NEM relay (in which the gate electrode of the NEM relay is connected in series to the ferroelectric capacitor) was investigated. As a result, a sub-0.5-V operating voltage is theoretically estimated.

Based on the polarization property and negative-capacitance (NC) effect of ferroelectric capacitors, nanoelectromechanical (NEM) diode nonvolatile memory cells (NC-NEM diode NVMs) are proposed for use in random-access memory arrays. It is observed that, by optimizing the structural parameters of the NEM memories, the NC-NEM diode NVMs can achieve more scaled program/erase voltages and better switching delays, when compared to the existing NEM diode memories. Moreover, the NC-NEM diode NVM has a one-directional current path, which is desirable in random-access memory arrays to block the sneak leakage.