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This work solves 3SAT, a classical NP-complete problem, on a CMOS-based Ising hardware chip with all-to-all connectivity. The paper addresses practical issues in going from algorithms to hardware. It considers several degrees of freedom in mapping the 3SAT problem to the chip - using multiple Ising formulations for 3SAT; exploring multiple strategies for decomposing large problems into subproblems that can be accommodated on the Ising chip; and executing a sequence of these subproblems on CMOS hardware to obtain the solution to the larger problem. These are evaluated within a software framework, and the results are used to identify the most promising formulations and decomposition techniques. These best approaches are then mapped to the all-to-all hardware, and the performance of 3SAT is evaluated on the chip. Experimental data shows that the deployed decomposition and mapping strategies impact SAT solution quality: without our methods, the CMOS hardware cannot achieve 3SAT solutions on SATLIB benchmarks.

A low-energy hardware implementation of deep belief network (DBN) architecture is developed using near-zero energy barrier probabilistic spin logic devices (p-bits), which are modeled to realize an intrinsic sigmoidal activation function. A CMOS/spin based weighted array structure is designed to implement a restricted Boltzmann machine (RBM). Device-level simulations based on precise physics relations are used to validate the sigmoidal relation between the output probability of a p-bit and its input currents. Characteristics of the resistive networks and p-bits are modeled in SPICE to perform a circuit-level simulation investigating the performance, area, and power consumption tradeoffs of the weighted array. In the application-level simulation, a DBN is implemented in MATLAB for digit recognition using the extracted device and circuit behavioral models. The MNIST data set is used to assess the accuracy of the DBN using 5,000 training images for five distinct network topologies. The results indicate that a baseline error rate of 36.8% for a 784x10 DBN trained by 100 samples can be reduced to only 3.7% using a 784x800x800x10 DBN trained by 5,000 input samples. Finally, Power dissipation and accuracy tradeoffs for probabilistic computing mechanisms using resistive devices are identified., Comment: ACM Great Lakes Symposium on VLSI (GLSVLSI), 2018

The emergence of semiconducting materials with inert or dangling bond-free surfaces has created opportunities to form van der Waals heterostructures without the constraints of traditional epitaxial growth. For example, layered two-dimensional (2D) semiconductors have been incorporated into heterostructure devices with gate-tunable electronic and optical functionalities. However, 2D materials present processing challenges that have prevented these heterostructures from being produced with sufficient scalability and/or homogeneity to enable their incorporation into large-area integrated circuits. Here, we extend the concept of van der Waals heterojunctions to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type amorphous indium gallium zinc oxide (a-IGZO) thin films that can be solution-processed or sputtered with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions exhibit anti-ambipolar transfer characteristics with high on/off ratios that are well-suited for electronic, optoelectronic, and telecommunication technologies., Comment: Manuscript (5 figures)+ supporting information, Nano Letters (2014)