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Tunnel field-effect transistors (TFETs) have garnered great interest as an option for the replacement of metal–oxide–semiconductor field-effect transistors owing to their extremely low off-current and fast switching suitable for low-power-consumption applications. However, conventional doped TFETs have the disadvantage of introducing undesirable random dopant fluctuation (RDF) events, which cause a large variance in the threshold voltage and ambipolar leakage current at negative gate voltages. In this study, a simple approach for charge plasma-based doping-less TFETs (DL-TFETs), including the Ge/Si bilayer frame, which affects the RDF and low on-current issues, was developed by the commercially available Silvaco Atlas device simulator. The use of the Ge/Si bilayer enhances the on-current and point subthreshold swing to 1.4 × 10−6 A and 16.6 mV dec−1, respectively. In addition, the dependencies of the Ge/Si junction boundary position and Ge content were examined systematically to attain a firm understanding of the electrical features in DL-TFETs. [ABSTRACT FROM AUTHOR]

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (Ion/Ioff) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ˝ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption). [ABSTRACT FROM AUTHOR]

The n + -base width of a two-terminal vertical thyristor fabricated with n ++ (top-emitter)-p + (base)-n + (base)-p ++ (bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n + -base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n + -base width. There was an optimal n + -base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n + -base width produced write/erase endurance cycles of ∼10 9 by sustaining a memory margin (I on /I off ) of 10 2 , and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a [Formula: see text] bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Thyristor random access memory without a capacitor has been highlighted for its significant potential to replace current dynamic random access memory. We fabricated a two-terminal (2-T) thyristor by wet chemical etching techniques on n + -p-n-p + silicon epitaxial layers, which have the proper thicknesses and carrier concentrations, as provided by technology computer-aided design simulation. The etched features such as etch rate, surface roughness, and morphologies, in a potassium hydroxide (KOH) and an isotropic etchant, were compared. The type of silicon etchant strongly affected the etched shapes of the side wall and therefore critically influenced the device performance with varying turn-on voltages. The turn-on voltage of thyristor fabricated with a KOH solution showed a consistent tendency of operation voltage in the range of 2.2-2.5 V regardless of the cell size, while the thyristor formulated with isotropic etchant had an operation voltage which increased from about 2.3-4.4 V as the device dimension decreased from 200 μm to 10 μm. The optimized 2-T thyristor showed a memory window of about 2 V, a nearly zero-subthreshold swing, and a current on-off ratio of about 10 4 -10 5 .