Search

Combinatorial optimization problems (COPs) are essential in various applications, including data clustering, supply chain management, and communication networks. Many real-world COPs are non-deterministic polynomial-time hard problems intractable using classical computers. Ising machine, the hardware accelerator based on the Ising model and annealing operation, has gained much attention as an alternative for solving COPs. The COPs are mapped to the Ising model, and their optimal/near-optimal solutions are explored by the intrinsic convergence property of the Ising machine. However, prior Ising machines based on locally connected spins have limitations in solving hard COPs due to significant overhead while mapping the Ising model to the inflexible hardware topology. In this work, we propose a scalable CMOS Ising machine with a network of flexible processing elements (PEs) to map and solve complex COPs with minimal overhead. The proposed Ising machine implements 256 PEs, where each PE is reconfigured to 1-to-4 spins with 28 spin interactions based on 8-bit coefficients. A 65-nm prototype chip has been fabricated, and a range of COPs have been mapped and solved, including max-cut and Boolean satisfiability problems.

This work presents a digital hardware accelerator with compute-near-memory to solve 2-D and 3-D partial differential equations (PDEs) using the finite difference method (FDM). The proposed hardware accelerator is reconfigured to solve 2-D/3-D Laplace and Poisson equations, and it scales to solve larger 2-D problems with no additional overhead. The reconfigurable and scalable architecture is implemented by building a 16 $\times $ 16 near-memory bit-serial processing element (PE) array and four 16 $\times $ boundary PEs with 92-kb static random-access memory (SRAM) distributed in the PE array. The proposed near-memory bit-serial computing architecture reduces data movement and achieves higher energy efficiency than the conventional Von Neumann architecture. The bit-serial computing architecture allows the PEs to communicate with neighbors via a minimal communication bandwidth (1 bit). The proposed hardware accelerator finds numerical solutions to 2-D PDEs (with up to a 64 $\times $ 64 grid size) and 3-D PDEs (with up to a 16 $\times $ 16 $\times $ 16 grid size) using FDM. A prototype chip is fabricated using 65 nm, occupying a 1.78-mm2 die area. The measured energy to solve the 2-D/3-D PDE for updating an entire grid is 0.7 nJ/1.14 nJ at 1 V and 25.6 MHz.

This article presents a novel dual 7T static random-access memory (SRAM)-based compute-in-memory (CIM) macro for processing quantized neural networks. The proposed SRAM-based CIM macro decouples read/write operations and employs a zero-input/weight skipping scheme. A 65nm test chip with $528\times 128$ integrated dual 7T bitcells demonstrated reconfigurable precision multiply and accumulate operations with $384\times $ binary inputs (0/1) and $384\times 128$ programmable multi-bit weights (3/7/15-levels). Each column comprises $384\times $ bitcells for a dot product, $48\times $ bitcells for offset calibration, and $96\times $ bitcells for binary-searching analog-to-digital conversion. The analog-to-digital converter (ADC) converts a voltage difference between two read bitlines (i.e., an analog dot-product result) to a 1-6b digital output code using binary searching in 1-6 conversion cycles using replica bitcells. The test chip with 66Kb embedded dual SRAM bitcells was evaluated for processing neural networks, including the MNIST image classifications using a multi-layer perceptron (MLP) model with its layer configuration of 784-256-256-256-10. The measured classification accuracies are 97.62%, 97.65%, and 97.72% for the 3, 7, and 15 level weights, respectively. The accuracy degradations are only 0.58 to 0.74% off the baseline with software simulations. For the VGG6 model using the CIFAR-10 image dataset, the accuracies are 88.59%, 88.21%, and 89.07% for the 3, 7, and 15 level weights, with degradations of only 0.6 to 1.32% off the software baseline. The measured energy efficiencies are 258.5, 67.9, and 23.9 TOPS/W for the 3, 7, and 15 level weights, respectively, measured at 0.45/0.8V supplies.

This brief introduces a current-mode DC-DC buck converter that operates without performance degradations, even when the inductance value changes. The proposed circuit can be widely utilized to ensure the stable operation of various systems, as inductor values in PMICs may fluctuate despite being identical components. The proposed Inductance-Variation-Insensitive (IVI) buck converter directly senses the rate of change of inductor current and transmits information about the output voltage and inductance to a dynamic ramp generator. The dynamic ramp generator produces a ramp signal proportionate to the sensed inductor current slope, thereby maintaining a deadbeat state and preventing subharmonic oscillations. This innovative approach enables the converter to function seamlessly across a wide range of output values while maintaining overall stability. The proposed buck converter is fabricated using a 0.18 $\mu $ m 1P6M CMOS process, occupying an active area of $0.82~mm^{2}$ . Experimental results demonstrate its stable operation over a broad range of output voltages, even in the presence of inductance variations, when compared to conventional fixed-ramp approaches. It exhibits a transient response recovery time of 3.9 $\mu $ s for a load change from 50 mA to 350 mA and 4.7 $\mu $ s for the reverse change, from 350 mA to 50 mA. Furthermore, this brief achieves a maximum power efficiency of 90.5%, accompanied by an output ripple of less than 30 mV.

Discovery is the key to unlocking the treasure chest of information that makes or breaks your client's case. Plaintiff lawyers tend to focus on their pursuit of--and expectations from--discovery from [...]