419 results on '"King, Ya-Chin"'
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2. A study of hydrogen plasma-induced charging effect in EUV lithography systems
3. High-density via RRAM cell with multi-level setting by current compliance circuits
4. Complementary Detectors for DUV Sensing by CMOS Logic Technology
5. A Study of Physical Unclonable Function by Dielectric Breakdown in High-κ Metal Gate Device
6. A New Ultra-Low Voltage Metal Fuse for High Density OTP Applications
7. Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology
8. CMOS-Compatible Embedded Artificial Synaptic Device (eASD) for Neuromorphic Computing and AI Applications
9. High-Density Embedded 3-D Stackable Via RRAM in 16-nm FinFET CMOS Logic Process
10. Application of twin-bit self-rectifying via RRAM with unique diode state in cross-bar arrays by advanced CMOS Cu BEOL process
11. Design of Wireless Multiple Gases Complementary Architecture Sensors Based on SnSe2 and PtSe2 Layered Films and Oscillating Circuits.
12. An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array
13. Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology
14. Wide range detector of plasma induced charging effect for advanced CMOS BEOL processes
15. Advanced self-convergent calibration for selenized 2D film gas sensors
16. FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems
17. Design of Versatile Top‐Down Transfer by Thermal Release Tape/Poly(methyl methacrylate) (TRT/PMMA) Bi‐Supporting Layers Toward All‐Transfer Transition Metal Dichalcogenide Material Based Transistor Arrays.
18. High Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications
19. Offset-Via Anti-fuse by Cu BEOL Process in Advanced CMOS Technologies
20. 16nm FinFET DUV Detector Array in Fully Compatible FinFET Logic Process
21. Characterization and Current Modeling of Stacked high-$\kappa$ Metal-Insulator-Metal Capacitors
22. On-Wafer FinFET-Based 3-D E-Beam Detector Cube for In Situ Monitoring of Advanced Lithography Processes Beyond 5 nm
23. A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications
24. 3-D Stackable Offset-Via Antifuse by Cu BEOL Process in Advanced CMOS Technologies
25. Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes
26. Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes
27. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
28. Retention Model of TaO/HfO x and TaO/AlO x RRAM with Self-Rectifying Switch Characteristics
29. A study of hydrogen plasma-induced charging effect in EUV lithography systems
30. Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory
31. 4K Detectors Array for On-Wafer EUV Imaging in Lithography Control Beyond 5-nm Node
32. A New Self-Powered Wireless Sensing Circuitry for On-Wafer In-Situ EUV Detection
33. Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays
34. A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model
35. Pure CMOS embedded Artificial Synaptic Device (eASD) for High Density Neuromorphic Computing Chip
36. 2T-Pixel Sensors Array for on-Wafer in-Chamber DUV Sensing
37. Self-Inhibit Complementary Cells by High-κ Metal Gate Transistors for Physical Unclonable Function
38. An Investigation of Plasma Charging Effect on FinFET Front-End-of-Line Processes
39. Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations
40. Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect
41. Multifunctional Ion‐Sensitive Floating Gate Fin Field‐Effect Transistor with Three‐Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology
42. Battery-Less Electronic Layer Detectors Array (ELDA) for In-Tool DUV Detection by FinFET CMOS Technology
43. Operation Optimization of Logic Compatible 2T RRAM Array by High-κ Metal Gate CMOS Logic Technologies
44. On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies
45. A Study of the Nonlinear Capacitance Variation in Inter Level Copper and Low-k Interconnect Structure
46. A study of gateless OTP cell using a 45 nm CMOS compatible process
47. On-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems
48. A Twin Bit AND-Type Multiple-Time-Programming Memory Cell by Nano-scaled High-κ Metal Gate Process
49. Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations.
50. Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect.
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