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Direct-etched HfO2/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO2/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO2 based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal gm the leakage is lower for HfO2 based transistors, despite the lower EOT for the HfO2 based devices.

In this paper, a model for describing tunneling from Si inversion layers is discussed. The model accounts for the quantization effects at the silicon/dielectric interface and is able to closely follow the self-consistent calculation of the potential and inversion charge in an inverted MOS structure. It is also applicable to multilayer gate stacks, since a general procedure is used for calculating the transmission through dielectric stacks. Influence of both material and geometrical parameters of a dual layer stack are discussed and scaling projections are inferred.

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel transistor to be equal. Scaling down the MOS transistor urges the need of including halo (or pocket) implants in the fabrication process. Due to this implant, however, the short channel MOSFET features a degraded effective mobility compared to the long channel reference device. This affects the channel-length extraction and results in unrealistic high values for the extracted effective channel-length for deep submicron transistors with high-dose halo (or pocket) implants.

We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.0 V are among the highest ever reported. The TaN metal gate electrode allows the capacitance equivalent thickness (CET or T/sub ox-inv/) to be scaled by 0.4 nm without increasing the gate leakage. A special metal etch stopping on 1.4 nm EOT SiON has been developed resulting in gate stacks of similar reliability as poly gate electrodes. We also report on an implant into the metal gate electrode that reduces gate leakage and increases mobility.

In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (HDD). We demonstrate that the triple junction has great potential in reducing significantly the variation of the device parameters such as drive current, off-state current, and overlap capacitance, originating from the non-uniformity of the offset spacer commonly used in CMOS devices below the 90 nm node.

High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperature stability. Various surface preparation methods and deposition conditions are tested. Compatibility of the high-k stacks with poly-Si and metal electrodes is investigated. Significant improvements in yield and thermal stability are obtained by optimized modifications of the high-k stack. Scaling of the equivalent oxide thickness (EOT) is accomplished by implementing novel ideas in interface engineering and high-k materials processing. High-k stacks are tested in transistor structures with small gate lengths. The origin of the electrical instabilities and the observed drive current degradation of high-k transistors as compared to the SiO/sub 2/ reference transistors are studied in detail.

The layout of FinFETs patterned with direct lithography and spacer lithography are analysed from a circuit density perspective. Requirements on the height of the fin to obtain competitive layout density are derived. Spacer lithography will be required to obtain the layout density targets with reasonable values of fin height.

A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device architectures (e.g., double-gate transistors, strained channels). We have optimized the process parameters and show that high-performance transistors can be realized, promising direct applicability of the results to future manufacturing.

We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.

Making use of SPER (Solid Phase Epitaxial Regrowth) As and B deep source/drain junctions with high activation can be obtained at temperatures below 700°C. However, higher thermal budget is required to regrow and activate the dopants in the poly gates. Low junction leakage and low contact resistance can be obtained for Ni-silicided As and B SPER junctions making use of deep As and B implants. Because of the low thermal budget source/drain junctions obtained by SPER are an attractive alternative to conventional spike annealed junctions for technologies making use of metal gates.

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

The creation of ultra-shallow junction for CMOS devices at the sub-100 nm node is driving significant efforts in developing thermal processing to give rise to high dopant activation in combination with limited diffusion. Flash-assist Rapid Thermal Annealing™ (fRTP™) is a promising new annealing technique, which involves the heating of the bulk of the wafer to an intermediate temperature using rather conventional spike RTP, followed by a short and intense pulse of light localized on the implanted wafer surface.In this work, we have systematically investigated the junction formation of different implants under fRTP anneals in terms of profile and devices. Co-implanted Ge and F species provide more box-like profiles with improved activation. Although leakage currents are higher for fRTP-annealed junctions than for spike-annealed junctions, appropriate fRTP process parameters and correct process conditions provide a critical tool to control and reduce the leakage current of co-implanted fRTP junctions to acceptable levels. Proper implant and anneal are requested for minimizing pattern effect and improving device performance.

An efficient yet accurate model is used for investigating tunneling of minority carriers from the inversion layer of ultrathin MOSFET structures. The model is derived from the concept of the quasibound states lifetimes, which are calculated using a transfer matrix method based on Airy functions. Comparison with experimental data is provided. Performance of high-k materials is discussed and an investigation of their scalability for future CMOS technology nodes is carried out.

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture.In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness (4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

This paper investigates the use of plasma nitridation (PN) for fabricating 1.5 and 2 nm gate dielectrics for CMOS system-on-a-chip (SoC) applications. The separate optimisation of PN recipes for high performance (HP, 1.5 nm) and low power (LP, 2 nm) CMOS devices results in good device performance with excellent device lifetime and low 1/f noise. For tripleoxide SoC applications, the use of a common PN step for both HP and LP yields gate dielectrics with excellent breakdown characteristics and devices with the required off-state leakage control.

An investigation of the gate stack for 90nm gate length CMOS is presented. The optimised 90nm nMOS and pMOS transistors exhibit state of the art DC and switching characteristics. Nominal nMOS and pMOS Ioff state current of 2nA / DD =1.2V) have been realized. An inverter delay of 15ps at 1.2V operating voltage has also been measured.

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In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (I on=450 µA/µm at I off=250 nA/µm for devices with L g\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.