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Concept for improving efficiency of photovoltaic solar cells based on decreasing p/n junction area in relation to total surface area of cell. Because of reduced junction area, surface leakage drops and saturation current density decreases. Surface passivation helps to ensure short-circuit current remains at high value and response of cells to blue light increases.

Lifetimes of minority carriers in silicon webs improved by annealing. Heat treatment of silicon web ribbons considerably improves efficiency of solar cells.

A silicon dendrite is grown as a ribbon forming two silicon crystal layers which are separated by an interface layer which contains a large number of defects. Significant increase of minority carrier lifetime with homogeneous distribution at the outer surfaces of the two silicon crystal layers is achieved by processing the web in an atmosphere of a selected gas, e.g., oxygen, nitrogen or an inert gas, for about 30 minutes to several hours at a temperature preferably on the order of 900 to 1200 C.

The economics and techniques for eliminating wafering as a part of ingot technology in the production of silicon sheets for photovoltaic applications are considered. Technical progress in both ingot and non-ingot technologies for the low cost solar array project is described in the context of process economics. The critical areas of research in wafering are delineated and their payoff potential discussed.

Fabrication of improved performance photovoltaic cells is described. They are fabricated from polycrystalline silicon containing copper segregated at the grain boundaries.

One of the goals of the national photovoltaic program in the U.S. is the establishment of an industry producing photovoltaic material which can be sold at a price not exceeding $0.70/W by 1986. A key element concerning the achievement of this goal is the development and utilization of improved methods for producing silicon sheet. Specific technologies being investigated in this connection can be divided into two categories. Methods of one category are based on a utilization of sheet growth techniques including film-fed growth, dendritic web, and silicon-on-ceramic processes. The approaches used by methods of the second category involve ingot and wafering processes, including Czochralski growth, the heat exchanger method, multiblade procedures, and the use of a fixed abrasive multiwire. It is found that using $84/kg silicon, most sheet technologies would yield module prices in the $2.00/Wp to $3.00/Wp range.

This study shows that the lower limits for manufacturing add-on costs to convert polysilicon to wafers is in the range of $22 to $26/sq m with the cost about equally divided between the crystal growth and wafering processes. However, the $22 to $26/sq m cost limit should be viewed as an asymptote since it is based on multicharge or continuous growth configurations, solidification rates in excess of 2 Kg/hr, multiblade wafering and a slice plus kerf of .045 cm. It should also be emphasized that the results of this study are based on as-sawn wafers, 100% yields (growth and slicing) and no profit. To the first approximation, the limiting cost factors are crucible material and furnace parts for growth and blade material and slurry for slicing.

To meet the need for low cost silicon sheet material in the ERDA/JPL photovoltaics program, JPL has initiated a wide ranging technology development effort in crystal growth that includes several different technology thrusts. They range in scope from innovative ingot growth and multislice wafering, to shaped growth techniques, substrate-related processes and hot forming techniques. In this paper, some salient observations on materials resulting from these processes are reported. Included are multiblade wafering-induced damage studies, interface morphology studies on the heat exchanger cast silicon, some diffusion length measurements in thin silicon layers on ceramic substrates, and results on the equilibrium structure found in laser zone ribbon growth.

Measurements of the non-uniform diffusion length of the minority carriers near grain boundaries in polycrystalline silicon have been used to develop an analytical model for the calculation of solar cell output as a function of grain size. Experimental results are presented which verify the theoretical analysis. Variation of open circuit voltage and fill factor with grain size is discussed.

The paper discusses structural defects in low-cost silicon sheets and their effect on the electronic properties related to solar cell performance. Experimental data are presented on the influence of grain boundaries on minority carrier diffusion length, impurity defect interaction, and variable surface recombination velocity. An analytical model of the effect of grain boundaries on solar cell performance is constructed based on these results.

The spatial variation of minority-carrier diffusion length in the vicinity of a grain boundary for a polycrystalline silicon sheet has been measured by the use of the EBIC technique. The effect of such a variation on solar-cell output has then been computed as a function of grain size. Calculations show that the cell output drops considerably for grain size smaller than three times the bulk diffusion length.

A correlation between the optimum etch loss and the depth of damage is established using wafers produced by the Multiblade Slurry (MBS) and the Internal Diameter (ID) saws. The observations are based on the measurement of the performance of solar cells fabricated on these wafers. Sample preparation and test results are described and the following conclusions are made: (1) the amount of silicon removal necessary for optimum solar cell performance coincides with the depth of saw-induced damage; (2) optimization of cell performance is not affected by the method of silicon removal; (3) sawing conditions should be optimized to minimize the extent of saw-induced damage; (4) the MBS saw is found to induce damage to a lesser extent; (5) since the extent of damage in MBS-sawn wafers is in the limit of etch loss required in texture etching, it is possible to achieve optimum improvement in cell performance by merely texture etching the surface of as-sawn wafers.

The presence of copper impurity, up to 10 to the 15th atoms/cc, in single crystal silicon has been shown to have no deleterious effect on the p-n junction solar cell performance. However, in polycrystalline silicon, copper atoms tend to migrate to the defect sites because of the structural sensitive properties of copper. This study was undertaken to investigate the influence of this behavior of copper impurity on the performance of p-n junction solar cells fabricated from structurally imperfect silicon. Two sets of polycrystalline silicon substrates containing copper were examined. In one set of samples, copper was incorporated during growth, whereas in the other, copper was diffused. Solar cells were fabricated on both the sets of substrates by a standard process. Dark and light I-V and spectral response characteristics of the cells were measured and compared with copper-free polycrystalline silicon solar cells. The results and the model are discussed.