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Fin field-effect transistor (FinFET) concept has been used to develop a new generation of vertical power devices based on gallium nitride (GaN) material. For the conventional GaN FinFET, the specific ON-resistance ( ${R} _{\text {on},\text {sp}}$ ) is still high, which imposes limitations on device design. In this article, a novel p-type nickel oxide (p-NiO) pillar GaN superjunction (SJ) FinFET is proposed. The proposed GaN SJ FinFET eliminates the issues of high ionization energy and low activation rate of impurities in p-type doping, realizes a new SJ charge compensation drift region, which greatly increases the breakdown voltage (BV) and reduces the ${R} _{\text {on},\text {sp}}$ of the device. In order to get highest figure of merit (FOM = BV2/ ${R} _{\text {on},\text {sp}}$ ), the parameters of the proposed device are optimized. Finally, the ${R} _{\text {on},\text {sp}}$ of the proposed GaN SJ FinFET and the conventional GaN FinFET are 0.274 and 0.969 $\text{m}\Omega \cdot $ cm2 respectively, which is reduced by more than 71%. And the threshold voltage is pushed forward to 2.25 V compared with 0.5 V of the conventional structure. The effect of incomplete ionization of NiO on the BV of the proposed device is also investigated. The proposed GaN SJ FinFET provides a new approach for realizing SJ devices on GaN material and has promising application prospects.

In this paper, a new ultra-low specific on-resistance quasi SiC MOSFET is proposed. Compared with the conventional SiC MOSFET, the proposed quasi SiC MOSFET has no problems caused by low channel mobility and gate oxide reliability. And compared with the conventional SiC JFET, the proposed quasi SiC MOSFET is a normally-off device without the controllability issue of the normally-on device. Through simulation, it is found that the specific on-resistance $(R_{\mathrm{ on,sp}})$ of the proposed quasi SiC MOSFET is 2.46m $\Omega \cdot $ cm 2, while the $R_{\mathrm{ on,sp}}$ of the conventional SiC MOSFET is 3.29 $\text{m}\Omega \cdot $ cm 2, with a reduction of more than 25% at almost the same breakdown voltage. In the forward conduction state, the saturation current of the proposed quasi SiC MOSFET is smaller than that of the conventional SiC MOSFET at $V_{\mathrm{ GS}}\,\,=$ 15V and 20V, which shows that the proposed quasi SiC MOSFET has a better safe operating area (SOA) and better short-circuit capability. Compared with the conventional SiC MOSFET, the Figure-of-Merit (FOM) of the proposed device is improved by 38%. In addition, since the proposed structure is sustaining voltage by the high voltage JFET cell without a gate oxide layer, it is suggested that the proposed device does not have gate oxide reliability problems.

In this article, we proposed a composite-barrier-metal–insulator–semiconductor-high electron mobility transistor (CB-MIS-HEMT), in which a thick AlxGa $_{({1}-{x}{)}}\text{N}$ with small Al mol fraction is implemented in the gate region to achieve both high threshold voltage ( ${V}_{\text {th}}{)}$ and high electron mobility. A Al $_{{0}.{25}}$ Ga $_{{0}.{75}}\text{N}$ /AlN, working as a second barrier, is set on the AlxGa $_{({1}-{x}{)}}\text{N}$ -layer to maintain high 2DEG density in the access region. The thick AlxGa $_{({1}-{x}{)}}\text{N}$ in the gate region reduces the mobility degradation effects caused by the interface charges, acoustic phonon scattering, and surface roughness scattering. Combined with small Almol fraction design, both low specific ON-resistance (Ron,sp)and high ${V}_{\text {th}}$ can be obtained simultaneously. An analytical model for the electron density in both the lower and upper channels as well as ${V}_{\text {th}}$ is presented, which matches very well with the experimentally calibrated TCAD simulation. For a 600-V design, it shows that the electron mobility in the lower channel can be improved to 1255 cm2/ $\text{V}\cdot \text{s}$ , and at ${V}_{\text {th}}$ around 2.5 V, Ron,sp of the CB-MIS-HEMT can be reduced by 33.6% compared to a conventional recess-gate MIS-HEMT.