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The characteristics of polysilicon resistors for CMOS ULSI applications have been investigated. Based on the presented sub-quarter micron CMOS borderless contact, both n+ and p+ polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyse and calculate some important parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance Rinterface, and pure sheet resistance Rpure. Furthermore, the characteristics of voltage-coefficient resistor, temperature-coefficient resistor, and resistor mismatching are also studied. An interesting sine-wave voltage-dependent characteristic due to the strong relation to the Rinterface has been modelled in this paper. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS ULSI technology.

We have investigated the interesting double ion implant (DII) Ti–salicide and pre-amorphization implant (PAI) Co–salicide techniques for ultra-large-scale integration (ULSI) applications. The DII technique is combined with germanium (or arsenic) PAI and Si ion-mixing processes. The sheet resistances both of n+ and p+ polysilicons are decreased when the DII Ti–salicide and PAI Co–salicide techniques are used. Moreover, the incomplete phase transformation of Ti–salicide is not observed in 0.2 μm wide polysilicon devices with the Ge DII process. Furthermore, the n+/p-well junction leakage current is reduced when the Si ion-mixing process is used. Experimentally, based on the studied DII Ti–salicide and PAI Co–salicide techniques, high-performance 0.2 μm CMOS devices have been successfully fabricated.

The effects of electrical and temperature stress on polysilicon resistors for CMOS technology applications are studied. Under a fixed square number, the peak current density (Jpeak) is increased with decreasing the polysilicon resistor width W. The time-to-fail value of the polysilicon resistor is decreased with increasing the electrical and temperature stress. A simple empirical formula is proposed in this study to predict the maximum current density (Jmax) and lifetime of polysilicon resistors. Under a fixed current density (1.0 × 106A cm − 2), the activation energies (Ea) for n + andp + polysilicon resistors at different temperatures are 0.67 and 0.48 eV, respectively. In addition, at a fixed temperature of 473 K, the current factors for n + andp + polysilicon resistors are 1.57 × 10 − 5and 1.30 × 10 − 5cm2 / A, respectively, under different current densities. Therefore, these precise reliability performances offer promise for ULSI design and fabrication.

A borderless contact (BLC) technique and double-implant structure (DIS) have been developed successfully to fabricate high-performance Ti-salicide sub-quarter-micron CMOS devices. A SiOxNy film grown by low-temperature chemical vapour deposition is used to act as the selective etch-stop layer. The n+ and p+ DIS can reduce the junction leakage current which is usually enhanced by BLC etching near the edge of shallow trench isolation. Based on the use of the BLC process, the process window can be enlarged. In addition, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. Experimentally, by combining the BLC and DIS techniques, low leakage and low sheet resistance CMOS devices and low standby current and high yield 1 Mb SRAMs are fabricated successfully.

The temperature-dependent characteristics of an n+-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n+-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1 x 100 μm2 device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of Vth from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and wide operation regime.

A novel photonic-sensitive InAlGaAs/InP negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) is fabricated and demonstrated. Due to the appropriately designed narrow base width and the employment of a δ -doped sheet at the emitter–base (E–B ) heterojunction, the base resistance effect results in the significant NDR phenomenon. In addition, the experimental results show that the device studied is very sensitive to the applied light source. The N-shaped NDR phenomena are clearly observed under illumination. This phenomenon is attributed to the base resistance and barrier lowering effect resulting from holes induced by the applied light source.

Temperature-dependent dc performances of lattice-matched InP/InGaAlAs heterojunction bipolar transistors (HBTs) using the InGaAlAs quaternary alloy as the base and collector layers are studied and reported. When compared with conventional InP/InGaAs HBTs, the device studied exhibits a higher common-emitter breakdown voltage and a lower output conductance even at high temperature. The variations of offset voltage and ideality factor at different temperatures have been analysed. In addition, with decreasing temperature from 25 °C toward -196 °C, an irregular temperature behaviour of current gain is observed. At high current levels, the temperature-dependent current gain is mainly determined by the reduced reverse hole injection current. As the current level is lowered, the dominance of reverse hole injection current is correspondingly replaced by the recombination current.

In this work, we report the temperature-dependent characteristics of a new InP/InGaAlAs heterojunction bipolar transistor (HBT). In order to improve the dc performance of conventional InGaAs-based single HBTs, the quaternary In/sub 0.53/Ga/sub 0.34/Al/sub 0.13/As with a wider bandgap is employed as the material for both the base and collector layers. Experimentally, the studied device exhibits a relatively high common-emitter breakdown voltage and low output conductance even at high temperature. Based on the breakdown mechanism of avalanche multiplication, the negative temperature dependence of breakdown voltage is attributed to the positive temperature-dependent impact ionization coefficient. Furthermore, the temperature dependence of current gain is investigated and reported. It is believed that the suppression of hole injection current with decreasing temperature is responsible for the opposite variation of current gains at high current levels.

The temperature-dependent characteristics of an InP/InGaAs superlattice-emitter resonant-tunnelling bipolar transistor have been studied and demonstrated. Due to the use of a five-period InP/InGaAs superlattice, the RT effect is observed at cryogenic temperature. In addition, the temperature-dependent dc characteristics of the studied device from room temperature to 398 K are reported. Dc current gain remains at an approximately constant value over the measured temperature range. The temperature coefficients of base-emitter and base-collector turn-on voltages are -2 and -3 mV K-1, respectively. The ideality factors of base current (nB) and collector current (nC) exhibit negative temperature coefficients. nB≈1 indicates that the bulk base recombination current component dominates the whole base current as the temperature is increased.

A novel multiple-state switching device based on an InP/AlInGaAs heterojunction bipolar transistor (HBT) structure has been successfully fabricated and demonstrated. The common-emitter current gain up to 25 is obtained under the forward operation mode. However, the anomalous multiple-negative-differential-resistance (MNDR) phenomena controlled either by electrical or optical input signals are observed under the inverted operation mode. The studied device exhibits a single-route S-shaped NDR behavior in the dark and a distinct significant S-shaped MNDR phenomena by introducing an incident light source at room temperature. Moreover, the anomalous multiple-route and multiple-step current-voltage (I-V) characteristics are also observed at 77 K. The switching behaviors are attributed to the avalanche multiplication, barrier lowering effect and potential redistribution process. Experimental results show that the studied device provides a good potentiality for multiple-valued logic and optoelectronic switching system applications.

Novel double delta-doped sheet (D3 S) Ga0.51 In0.49 P/In0.15 Ga0.85 As/Ga0.51 In0.49 P pseudomorphic high-electron-mobility transistors (PHEMTs) have been fabricated successfully and studied. A wide-gap Ga0.51 In0.49 P Schottky layer and a D3 S structure are used to improve device performance. Furthermore, an airbridge-gate structure is employed to achieve good dc and RF performances. For a 1 µm gate length device, a high gate-to-drain breakdown voltage over 35 V, an available output current density up to 615 mA mm-1 , a maximum transconductance of 110 mS mm-1 and a high dc gain ratio of 487 are obtained. On the other hand, the maximum values of unity current gain cut-off frequency fT and maximum oscillation frequency fmax are 19.5 and 40.5 GHz, respectively. The output power of 15.6 dB m (363 mW mm-1 ), power gain of 5.6 dB, power added efficiency (PAE) of 37% and drain efficiency (DE) of 51% are obtained at an input power of 10 dB m and the measured frequency of 2.4 GHz.

A new and interesting negative-differential-resistance heterojunction bipolar transistor (NDR-HBT) based on the InP/InAlGaAs material system is fabricated successfully and demonstrated. Due to the employment of narrow base and /spl delta/-doped sheet at the emitter-base (E-B) heterojunction, the significant and interesting topee-shaped current-voltage (I-V) characteristics are observed in the low current regime. A peak-to-valley current ratio (PVCR) up to 11 in the NDR loci is found. In the higher current regimes, on the other hand, NDR phenomena disappear and the device acts as a normal bipolar transistor. These interesting properties are believed to be attributed mainly to the modulation of potential spike resulting from the specified device structure.

In this paper, a novel InGaP/GaAs multiple S-shaped negative-differential-resistance (NDR) switch based on a heterostructure-emitter bipolar transistor (HEBT) structure is fabricated and demonstrated. An interesting multiple NDR phenomenon resulting from an avalanche multiplication and successive two-stage barrier lowering process is observed under the inverted operation mode. The three-terminal-controlled and temperature-dependent NDR characteristics are also investigated. In addition, a typical transistor performance is found under the normal operation mode. Consequently, owing to the presented different stable operation points and transistor action, the studied device shows a good potential for multiple-valued logic and analog amplification circuit applications.

We have fabricated and discussed the performances of the InGaP GaAs and AlGaAs GaAs HEBTs. From the calculation, an emitter thickness not smaller than 230 and 320 A is needed to eliminate the emitter-base (E-B) potential spike for an InGaP GaAs and an AlGaAs GaAs HEBTs, respectively. For the studied InGaP GaAs HEBT, a wide emitter thickness of 700 A degrades the d.c. performance due to the bulk recombination effect in the emitter neutral region under the large E-B forward bias. In addition, we observe a multiple S-shaped NDR resulting from an avalanche multiplication and successive barrier lowering process as operated in the inverted mode. Whereas the AlGaAs GaAs HEBT with an emitter thickness of 500 A is properly designed to obtain a high current gain and a low offset voltage. However, we observe only a single S-shaped NDR for the AlGaAs GaAs HEBT. This is due to the barrier lowering effect attributed to the fact that the hole's and electron's accumulation occur simultaneously. Both the transistor action in normal operation mode and the presence of NDR make our studied devices very promising for the analog and logic circuit applications.

A metal-insulated-semiconductor (MIS) like In 0.2 Ga 0.8 As GaAs doped-channel structure has been proposed. Furthermore, a field-effect transistor (FET) based on the proposed structure is also fabricated. Both theoretical simulations and experiments are made and compared in this paper. First, the theoretical analysis by using the self-consistent method with a quadratic expression of the charge control process is employed to simulate the basic electronic properties of the doped-channel FET. From the simulation results, we can find that the d.c. performances show good transistor characteristics. For the experimental results, a high breakdown voltage of 17.4 V, a maximum drain saturation current of 930 mA/mm, a maximum transconductance of 235 mS/mm, and a very broad gate voltage range larger than 3 V with the transconductance higher than 200 mS/mm are obtained for a 2 × 100 μm2 gate-dimension FET. From the comparison, we find that experiment results are in a good agreement with the theoretical simulations. The performances provide a promise of the proposed device to be a good candidate for practical circuit applications.

The temperature-dependent characteristics of polysilicon and diffused resistors have been studied. By using 0.18-/spl mu/m CMOS technology, a cobalt salicide process is employed and silicide is formed at the ends of resistors. Based on a simple and useful model, some important parameters of resistors including bulk sheet resistance (R/sub bulk/) and interface resistance (R/sub interface/) are obtained at different temperature. For diffused resistors, the R/sub bulk/ and R/sub interface/ values increase and decrease with increase of temperature, respectively. Positive values of temperature coefficient of resistance (TCR) are observed. Furthermore, TCR values decrease with decreasing resistor size. For polysilicon resistors, the R/sub interface/ values decrease with increase of temperature. In addition, negative and positive TCR values of R/sub bulk/ are found in n/sup +/ and p/sup +/ polysilicon resistors, respectively. In conclusion, by comparing the studied diffused and polysilicon resistors, negative trends of TCR are observed when the resistor size decreases.

A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications has been demonstrated and studied. A simple model is proposed to analyze its important parameters such as the voltage-dependent bulk sheet resistance, interface resistance, and voltage coefficient of resistance (VCR). An anomalous voltage-dependent characteristic of overall resistance is found to mainly result from the existence of interface resistance. The proposed structure of a polysilicon resistor with a larger effective width of interface region shows substantial suppression of the voltage-dependent resistance deviation caused by interface resistance. The reduction of the VCR value is also obtained for the new structure. Consequently, from experimental results, the proposed structure can be used in precise (lower VCR) polysilicon resistors.

The characteristics of polysilicon resistors in sub-0.25 /spl mu/m CMOS ULSI applications have been studied. Based on the presented sub-0.25 /spl mu/m CMOS borderless contact, both n/sup +/ and p/sup +/ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(/spl Delta/W), interface resistance R/sub interface/, and pure sheet resistance R/sub pure/. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 /spl mu/m CMOS technology.

A novel double ion-implant Ti-salicide technology combining As pre-amorphization implant plus Si ion-mixing implant without the additional lithography process has been developed successfully and reported. Based on this technology, the good performances of uniform Ti-silicide formation, low and narrow distribution of sheet resistances both on n/sup +//p/sup +/ poly-gate and source/drain diffusion layers, and lower leakage currents in the n/sup +//p-well and p/sup +//n-well junctions are obtained simultaneously. In addition, excellent behavior of a 0.24-/spl mu/m NMOSFET and PMOSFET fabricated by this technology are also achieved.

We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO/sub x/N/sub y/ film to act as the selective etching stop layer and the additional n/sup +/ and p/sup +/ source-drain double implant structure (DIS) are employed in the studied device. The additional n/sup +/ and p/sup +/ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration.

An interesting multiple S-shaped negative-differential-resistance (NDR) phenomenon is observed for an InGaP/GaAs heterostructure-emitter bipolar transistor (HEBT) under the inverted operation mode. This behavior results from a sequential avalanche multiplication and two-stage barrier lowering effect. The two-stage barrier lowering effect is assumed to be caused by the high valence-band-discontinuity (/spl Delta/E/sub v/) to conduction-band-discontinuity (/spl Delta/E/sub c/) ratio at InGaP/GaAs heterointerface which gives holes and electrons accumulation effect successively. Under normal operation mode, a typical common-emitter current gain of 60 is obtained at collector current density of 400 A/cm/sup 2/ for the studied HEBT without emitter-edge thinning structure. Consequently, the controlled switching and transistor performances provide a promise of the studied device for circuit applications.

The temperature-dependent characteristics of polysilicon and diffused resistors have been studied. By using the 0.18 /spl mu/m CMOS technology, cobalt salicide process is employed and silicide is formed at the ends of resistors. Based on a simple and useful model, some important parameters of resistors including bulk sheet resistance (R/sub bulk/) and interface resistance (R/sub interface/) are obtained at different temperature. For diffused resistors, the R/sub bulk/ and R/sub interface/, values are increased and decreased with the increase of temperature, respectively. Positive values of temperature coefficient of resistance (TCR) are observed. Furthermore, TCR values are decreased with the decrease of resistor size. For polysilicon resistors, the Rinterface values are decreased with the increase of temperature. In addition, negative and positive TCR values of RNA are found in n/sup +/ and p/sup +/ polysilicon resistors, respectively. In conclusion, by comparing the studied diffused and polysilicon resistors, the negative trends of TCR are observed when the resistor sizes are decreased.

A GaAs/n+‐In0.2Ga0.8As/GaAs doped‐channel field‐effect transistor structure has been fabricated and studied. A typical transistor performance with a threshold voltage of about −3.0 V and transconductance of up to 160 mS/mm is obtained in the lower gate‐source voltage (VGS

A high-barrier gate GaInP/GaAs doped channel field-effect transistor (DCFET) has been fabricated and studied. The /spl delta/(P/sup +/)GaInP layer is employed to offer a high conduction band offset for a good electron confinement and achieve a high valance band offset as a hole barrier. The active channel is triple-step doped to obtain high-barrier camel gate. A fabricated n/sup +/-GaAs//spl delta/(P/sup +/)GaInP/n-GaAs camel diode exhibits a barrier height larger than 1.2 eV and a very high breakdown voltage of 33 V. The measured transconductance is 140 mS/mm with a unity current gain frequency of 17 GHz for a 1/spl times/50 /spl mu/m/sup 2/ device.

In this paper we fabricate a GaAs/n/sup +/InGaAs/GaAs doped-channel FET device with significant transistor performance. The use of the doped-channel structure also has the benefits of: (1) enhanced electron mobility and velocity in the InGaAs channel; and (2) elimination of the undesired DX centers or persistent photoconductivity effect. Study of the structure reveals that it exhibits the anomalous negative differential resistance (NDR) phenomenon. We conclude that the NDR performance is related to the existence of deep-level electron traps and the real-space transfer effect. Because only part of the fabricated devices exhibit NDR phenomena, the nonuniformly distributed deep-level electron traps related to the substrate or MOCVD growth process may be expected. The existence of electron traps enhances the decrease of channel current resulting from the real-space transfer effect. When the channel electrons gain enough energy from the accelerating field (at higher V/sub DS/ regime), they may inject into the neighboring GaAs layers and become trapped in the deep levels. This causes the reduction of conduction current and occurrence of NDR behavior.

The temperature-dependent characteristics of silicon diffused resistors are demonstrated and studied. Based on the presence of a silicide/silicon junction, the device size plays an important role on diffused resistor behaviours. From experimental and theoretical analysis, some important parameters, e.g. the interface resistance (R/sub interface/), sheet resistance (R/sub bulk/), deviations of resistor length (/spl Delta/L) and width (/spl Delta/W ) are obtained. Also, anomalous phenomena of temperature coefficient of resistance (TCR) are found.

A highly hydrogen-sensitive Pd/InP metal-oxide-semiconductor (MOS) Schottky diode hydrogen sensor is presented. The role of donor level in the interfacial oxide layer replacing the amphoteric native defects leads to enhanced barrier height and high sensitivity. According to reaction kinetics studies, the maximum change in barrier height achieves 0.31 eV. Short response and recovery times in the transient characteristics demonstrate the high hydrogen adsorption and desorption rates at high temperatures.

In this work, a new InGaP/GaAs heterostructure transistor with a □-doped wide-gap collector structure has been fabricated successfully and demonstrated. A near-ideal breakdown characteristic and good transistor performance are obtained. These good characteristics are mainly due to the complete elimination of potential spike at emitter-base (base-collector) heterojunction and the employment of wide-gap InGaP material as collector layer. Consequently, the studied device shows a promise for high-speed and large input signal circuit applications.

A new high-performance Ga0.51In0.49P/In0.15Ga0.85As pseudomorphic heterostructure field-effect transistor (PHFET), based on a novel airbridge-gate structure with multiple piers, has been studied. Due to the employment of high Schottky barrier GalnP layer and the newly designed double delta-doped sheets (D3S) InGaAs channel, the high gate-to-drain breakdown voltage and broad and linear transconductance are obtained simultaneously. Also, the use of airbridge-gate technique may improve the DC and RF characteristics of device by suppressing the gate leakage current and reducing the parasitic capacitance.

The temperature-dependent characteristics of InGaP/In x Ga1-x As/GaAs pseudomorphic transistors with an inverted delta-doped V-shaped channel have been studied. Due to the presented wide-gap InGaP Schottky layer and the V-shaped channel structure, the degradation of device performance with increasing the temperature is not so significant. Experimentally, for a 1×100 µm2 device, the gate-drain voltages at a gate leakage current of 260 µA/mm and the maximum transconductances g m,max are 30 (22.2) V and 201 (169) mS/mm at the temperature of 300 K (450 K), respectively. Meanwhile, the broad and flat drain current operation regimes for high g m, f T, and f max are obtained.

We review the current investigation of heterostructure-emitter bipolar transistors (HEBT) and pay attention to confinement effects on the common-emitter current gain and the occurrence of negative-differential resistance (NDR). Three main devices with different heterostructure emitters have been grown and discussed. These devices include single-(SHEBT), double-(DHEBT), and resonant tunneling-(RT-HEBT) structure with Al 0.5 Ga 0.5 As/500A-GaAs, Al 0.5 Ga 0.5 As/500A-GaAs and 5-period 50A-Al 0.5 Ga 0.5 As/50A-GaAs superlattic emitters, respectively. With respect to current gain, it is found that Al 0.5 Ga 0.5 As/500A-GaAs gives the best confinement effect on hole minority carriers We obtain common-emitter current gains of 180, 18, and 65 for the SHEBT, DHEBT and RT-HEBT, respectively. Besides, all of the studied devices exhibit an interesting S-shaped negative-differential resistance (NDR) resulting from the regenerative switching process. With respect to NDR performance, the Al 0.5 Ga 0.5 As/500A-GaAs, shows the best confinement effect on the ionized electrons. The controlled voltage efficiencies are 1.43, 1.77, and 1.12 for SHEBT, DHEBT, and RT-HEBT, respectively.