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This work aims to optimize Plasma-Enhanced Chemical Vapour Deposition (PECVD) amorphous hydrogenated silicon carbide (a-SiC:H) as a conformal passivation layer for invasive microelectrode array (MEA) neural interface applications. By carefully tuning the PECVD deposition parameters, the composition, structure, electrical, and mechanical properties of the films can be optimized for high resistivity, low stress, and great resistance to chemical attack. This optimization will eventually allow a-SiC:H to be used as an ideal insulation, passivation and protection layer for thin and biocompatible all-SiC neural interfaces.

In this paper, a suitable process technology is employed to fabricate a new open gate silicon carbide-based junction field-effect transistor (OG-4H-SiC-JFET) intended to be used for all types of biochemical sensing applications. The main focus is dedicated to the fabrication steps and specifically the plasma etching of the SiC as it is the key step to pattern the device components. All necessary I-V characteristics (IDS-VDS and IDS-VGS) have been derived and show acceptable electrical performance. Furthermore, the electrical characteristics of the OG-4H-SiC JFET were simulated using 3D Silvaco ATLAS and are in line with the experimental electrical characteristics. The efficacity and simplicity of the process described in this paper is the first step for future development of biochemical sensors based on SiC-FETs.

A SiCNWFET device serving as a biosensor was designed and simulated using Silvaco ATLAS device simulation software. The performance of the designed device in charges sensing was investigated. The device shows the ability to recognize different interface charge values ranging from-1.10E11 to-5.10E12 cm-2 applied on the surface of the silicon carbide nanowire channel to simulate target charge biomolecules that bound to the biosensor. A significant change in the output current is observed due to the presence of different values of fixed interface charge densities. An optimum, according to the TCAD simulation, the 4H-SiC epitaxial structure has been grown. The designed device was fully fabricated on this structure and it exhibited acceptable electrical characteristics.

A comparative study of the simulated breakdown voltage of 4H-SiC devices has been conducted for the most widely used impact ionization models (Selberherr, Hatakeyama), based on the experimental data of 4H-SiC pn diodes. The effect of mesh density on the simulated breakdown voltage has been examined. The TCAD simulations employing default commercial simulators parameters did not converge to a value close to the experimentally observed as the mesh density is increased. Various experimental ionization parameters, as reported in the bibliography, have been examined instead of the commercial-TCAD-simulators default ones. Simulations with optimal parameters result in convergence to breakdown voltage values close to the experimentally measured ones when the mesh density is increased.

Secondary electron imaging of SiC epi-structures is commonly used as it allows doping topography i.e. the knowledge of the spatial extension of differently doped layers. Determination of the doping level of the layers was not possible until now. The present work presents how to use this technique for 4H-SiC p-type doping determination. This is indeed, possible for specific experimental data analysis and for doping levels higher than 1017cm-3.

This paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (CGS) and gate-drain (CGD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. CGSand CGDare modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET.

International audience; Different methods for cross-section doping topography of SiC Trenched-singly-implanted vertical junction field effect transistors (TSI-VJFETs) are presented with the purpose to determine the doping distribution in the epitaxial structure and the implanted areas.

Internal device capacitances in 4H-SiC based devices play an important role in determining their performances. In the present work, an analysis of the capacitance measurements in 4H-SiC trenched and single-implanted (TSI) gate vertical JFET TSI-VJFETs has been undertaken. Physical parameters such as threshold voltage and the related to its value effective channel length as well as channel layer and drift layer doping profiles have been extracted. The measured internal capacitances have been modeled by various models based on device physics.

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Purely vertical 4H-SiC JFETs have been modeled by using three different approaches: the analytical model, the finite element model and the compact model. The results of the modeling have been compared with experimental results on a series of fabricated self-aligned devices with two different channel lengths (0.3 and 1.1μm) and various channel widths (1.5, 2, 2.5, 3, 4 and 5 μm). For all the considered models I-V and C-V characteristics could be satisfactorily simulated.

The threshold voltage of SiC JFETs has been determined from transfer characteristics by employing methods commonly used in the case of MOSFETs. The extracted values have been compared with the value determined from the fitting of experimental transfer characteristics with the Schockley model equation. Moreover, the variation of the extracted threshold voltage values with respect to channel width has been employed to determine the channel concentration without taking into account the Vbi value.

Si nanowires (NWs) samples have been converted to silicon carbide (SiC) NWs at different conditions of substrate temperature in an ultra-high vacuum using a molecular beam epitaxy (MBE) set-up. Auger electron spectroscopy (AES) and reflection high-energy electron diffraction (RHEED) have been in-situ carried out to control the growth process. Scanning electron microscopy (SEM) and conventional transmission electron microscopy (CTEM) have been used to characterize the resulting nanostructures. In addition, the samples have been prepared by focused ion beam (FIB) in order to have electron-transparently lamellas for TEM with the interface nanowire-substrate. SiC/Si shell/core NWs free of planar defects have been obtained for conversion tmpratures lower than 800oC.

A systematic study of the usually employed models of 4H-SiC bandgap energy value and carrier mobility in TCAD simulations has been performed. Theoretically calculated and experimentally determined values of these parameters are compared with the corresponding models used in TCAD simulations of different research groups as well as of related software developer SILVACO. Comparisons between physical and established semi-empirical models have been made and deviations from the experimental values are observed in many reported studies. Based on this analysis, the best fitting models and the corresponding coefficients are proposed.

The process technology for the fabrication of 4H-SiC trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) has been developed. The optimized TIVJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. A source-pillars sidewall oxidation and subsequent removal of the metallization from the top of the sidewall oxide ensured isolation between gate and source. Optimum planarization of the source pillars top has been performed by cyclotene spin coating and etch back. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The voltage blocking exhibits a triode shape, which is typical for a static-induction transistor (SIT) operation. The transistors exhibited high ON current handling capabilities (Direct Current density >1kA/cm2 ) and values of RON ranging from 6 - 12 mΩ•cm2 depending on the channel length. Maximum voltage blocking was 800V limited by the edge termination. The maximum voltage gain was 51. Most transistors were normally-on. Normally-off operation has been observed for transistors lower than 2μm channel width (mask level) and deep implantation.

The purpose of the present study is to study the crystal periodicities that appear in 4H- and 6H-SiC material after the implantation with nitrogen and prior to post-implantation annealing. High Resolution X-Ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM) have been employed towards this purpose. Extra peaks at smaller, than the main (00n) peak, diffraction angles in HRXRD scans and extra spots in the electron diffraction patterns have been observed due to the presence of these periodicities. Higher lattice constant periodic structures are apparently formed from the implanted nitrogen ions located at interstitial sites and disappear after the annealing and the resulting positioning of nitrogen atoms in substitutional sites.

The process technology for the fabrication of 4H-SiC Static Induction Transistors (SITs) has been developed. Conventional contact UV lithography and self-aligned techniques have been employed. Al-outdiffusion following Rapid Thermal Annealing (RTA) has been determined as the cause for the increased reverse leakage and early forward turn-on of the gate-source junction. The fabricated transistors, exhibited a specific RON value in the region of 2mΩ•cm2 and 80 V turn-off voltage.

Back-gated field effect transistors (FETs) based on 3C-SiC nanowire (NW) were fabricated and the electrical characterization revealed devices with either ohmic or rectifying contacts leading to two different operation modes. The transistors with ohmic-like contacts manifest very weak gating effect and the device switching off is not achievable even for high negative gate voltages due to the high electron concentration along the nanowires. In contrast, the devices with Schottky contact barrier at Source / Drain regions demonstrate a well determined switching off and in general better performance thanks to the modulation of the drain current through the control of Schottky barriers transparency at the source and drain regions. Nevertheless, ohmic contact devices are expected to demonstrate even better performance if the NW material quality as well as the quality of the interface with the gate oxide is substantially improved.

Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and the electrical characterization revealed electron conduction through the NWs. Devices with either ohmic or rectifying contacts have been observed leading to two different operation modes. The transistors with ohmic-like contacts manifest a very weak gating effect and the device switching OFF is not achievable even for high negative gate voltages due to the high electron concentration along the NWs. In contrast, the Schottky contact barrier (SB) at source (S)/ drain (D) regions acts beneficially for the FET performance by suppressing the off current. At high positive gate voltages (>;20 V), the SBs tend to be more transparent leading to ION/ IOFF ratio equal to ~103 in contrast to the weak gating effect of the ohmic contact 3C-SiC NWFETs. Therefore, in the case of highly doped NWs, where the direct effect of the gate voltage on the accumulated carriers is negligible, SB-NWFET presents improved performance by suppressing the off current and indirectly modulating the drain current through the control of SBs transparency at source and drain regions.

Silicon microwires (MWs) previously synthesized using the VLS method with gold catalyst are being carburized at 1100°C under methane aiming to their conversion to SiC. SEM, TEM as well as XPS and Raman spectroscopy were used for structural and morphological characterization. After carburization achievement, SiC is found to be polycrystalline with a high density of stacking faults associated to an increase of surface roughness. Directions for the carburization process optimization are given.

Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowire (NW) were fabricated. Devices with rectifying Source (S) and Drain (D) contacts have been observed. In contrast with the ohmic-like devices reported in the literature, the Schottky contact barrier (SB) at S/ D regions acts beneficially for the FET performance by suppressing the off-current. At high positive gate voltages (>10 V), the Schottky barriers tend to be more transparent leading to ION/IOFF ratio equal to ~ 103 in contrast to the weak gating effect of the ohmic-contacted 3C-SiC NWFETs.

Back-gated field effect transistors (FETs) based on catalyst-free grown 3C-SiC nanowires (NWs) were fabricated and electrical characterization is presented. Silvaco simulation was used to fit the I-V characteristics and to extract information about the carrier (electrons) concentration and the oxide/NW interface quality. The high trap density and fixed charges at the nanowire/oxide interface, Dit~5x1011 cm-2eV-1 and Qf ~3x1013cm-2, and the high electron concentration (~3x1019 cm-3) originating from unintentional doping severely affect the electrical conduction through the nanowires which has as a result low values of mobility and transconductance, 0.11 cm2/Vs and 7x10-10 A/V, respectively.

The behavior of 200nm Cr Schottky contacts on n-type 4H-SiC has been investigated with photoelectron spectroscopy (XPS) and standard (I-V and C-V) electrical measurements at different measurement temperatures. A barrier height close to 1.2 eV was calculated from XPS data under no-current and no-bias conditions on ultra-thin Cr films grown in-situ under UHV conditions. The I-V measurements on as-deposited contacts resulted in a barrier height of 1.06 eV while a value of 1.2 eV has been extracted from the C-V measurements.

In this work, SiC nanowire (NW) FETs are prepared and their electrical measurements are presented. From the samples fabricated on the same substrate, various I-Vs shapes are obtained (linear, non linear symmetric, and asymmetric). With the assistance of simulation, we show that this is a result of different values of Schottky Barrier Heights (SBH) at Source (S) / Drain (D) contacts of FETs. An origin for this might be a non uniformity in annealing, NW doping level and high interface traps density (that pins the Fermi level) as well as the high sensitivity of the metal-NW contacts to local surface contaminations.

Cr/4H-SiC Schottky contacts were investigated by standard electrical measurements and photoelectron spectroscopy. XPS (X-ray Photoelectron Spectroscopy) measurements were performed during the in-situ formation of the metal-semiconductor interface formation as well as after several annealing steps of the Cr/4H-SiC contact. A barrier height of 1.2 eV was determined from XPS measurements. The electrical measurements have showed the necessity of thermal annealing at 600 °C to obtain best performance (ΦB = 1.05 eV from C-V measurements and 0.94 eV from I-V measurements with ideality factor n = 1.08).

3C-SiC is a promising material for high power and high-speed electronic devices as well as in sensors operating at high temperatures or hostile environments. For these reasons, we solved self-consistently the Poisson equation within the quantum Non Equilibrium Green Function Formalism (NEGF) in order to model and compare 3C-SiC and Si nanowire (NW) Field Effect Transistors (FETs) operating in ballistic regime (at room temperature 300 K). As a general conclusion of our calculations, Si and SiC NW FETs have almost the same electrical behavior: they depict the same subthreshold slope and have similar on currents [ION/IOFF (SiC)~81 % ION/IOFF (Si) in case of 4 nm NW cross section side].

Multi-diode broadband microwave signal modulators based on 4H-SiC p-i-n diodes were fabricated and fully characterized. The three-diode modulators are characterized by a transmission loss of 1-2 dB and isolation of 27-34 dB in the 2-7 GHz frequency range. Two-diode modulators were specially designed for high-temperature operation. These modulators are characterized by a transmission loss of 1.1-2.6 dB and isolation of 33-44.5 dB, in the 2-7 GHz frequency range at temperatures up to 300°C.

We have successfully demonstrated p-type silicon nanowire field-effect transistors (Si NW p-FETs) prepared using B-ion implantation with a dose of 1 × 1013 ions/cm2 and an energy of 10 keV. The experimental ID−VDS characteristics for B-implanted Si NW FETs revealed a clear p-channel FET behavior with a hole mobility of ∼6.9 cm2/(V·s), a hole concentration of ∼1.1 × 1019 cm−3, and a transconductance of ∼29 nS/μm at a VDS of 0.1V. The B-implanted Si NWs were annealed at a temperature of 950 °C for 30 and 60 s. The 2D-ATHENA and ATLAS software were used to accurately simulate the device fabrication process and the electrical performance, respectively.

4H-SiC p-i-n diodes were designed, fabricated and characterized for use in microwave applications. The diodes exhibited a blocking voltage of 1100 V, a 100 mA differential resistance of 1-3 &, a capacitance below 0.5 pF at a punchthrough voltage of 100 V and a carrier effective lifetime between 15-27 ns. Single 4H-SiC p-i-n diode switches, operating in X-band, exhibited insertion loss 0.7 dB, isolation up to 25 dB and were able to handle microwave power up to 2.2 kW in pulsed mode of operation. The switching speed of the switches has not exceeded 20 ns.

A classical implementation of the field plate technique is the oxide ramp termination. This paper presents for the first time a comparison between SiC and diamond Schottky barrier diodes (SBD) using this termination. The influences of the ramp angle and oxide thickness on the diodes electrical performance are investigated for both punch-through (PT) and non punch-through (nPT) structures. The efficiency of the termination is also evaluated.

4H-SiC p-i-n diodes were fabricated on epitaxial layers grown by Sublimation Epitaxy in Vacuum (SEV) and were evaluated for microwave power switching applications. Full electrical characterization (C-V, DC I-Vs, reverse recovery characteristics, low and high power microwave testing) has been performed. The results showed that SEV-grown SiC material is suitable for bipolar device fabrication. A doping higher than 1019 cm-3 for the p-type contact layer and lower than 1016 cm-3 for the n-type base layer is necessary to demonstrate microwave p-i-n diodes with similar performance as the ones fabricated on commercially available CVD-grown material.

International audience; Raman spectroscopy and photoemission microscopy were coupled as two complementary non-destructive optical techniques in order to study biased 4H-SiC pin diodes. These two characterization tools have been largely used for the study of semiconductors but the combination of these two techniques has hardly been reported so far. Some structural defects inducing the same electrical damage could be discriminated and identified. Temperature could be measured in operating devices and the influence of the diode operating mode on the Raman signal could be evidenced.

Pulsed-laser-based methods have been applied for post-implant annealing of p-type Al-doped 4H–SiC wafers in order to restore the crystal structure and to electrically activate the doping species. The annealing was performed with the third harmonic (355 nm) of a Nd:YAG laser at 4 ns pulse duration. The epilayers were characterized by micro-Raman spectroscopy under surface and cross-sectional backscattering. Changes in the phonon mode-intensity were related to the laser annealing induced recrystallization of the implanted material. The results were compared with changes in the infrared reflectivity across the Reststrahlen band. Transmission electron microscopy analysis showed the formation of columnar polycrystalline structure after the laser annealing process.

In the range 80 K-900 K, we have investigated the electrical properties of heavily aluminum in-situ doped, 4H-SiC samples. The temperature dependence of the hole concentration and Hall mobility was analyzed in the model taking into account heavy and light holes. The modelisation parameters were compared with experimental values of Secondary Ion Mass Spectroscopy (SIMS) and Capacitance-Voltage (CV) measurements.

International audience; The until-now demonstrated SiC-Nanowire Field Effect Transistors (NWFETs) have exhibited poor performance due to the high residual doping of the NWs as well as the bad interface with the gate dielectrics. Top-down NWs have been used for the SiC NWFETs fabrication on the basis of low-doped 3C-SiC material and eliminating, thus, the first reason. The transistors with top-down grown NWs exhibited three orders of magnitude higher current and transconductance values with respect to SiC NWFETs with bottom-up grown NWs. Nevertheless, it was not possible to switch-off the transistors showing the importance of interface with the gate dielectrics.

Trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The transistors exhibited high current handling capabilities (Direct Current density 330A/cm2). The output current reduces with the increase of the measurements temperature due to the decrease of the electron mobility value. The voltage breakdown exhibits a triode shape, which is typical for a static-induction transistor operation.

A 248 nm (KrF) excimer laser with a repetition rate of 10 Hz, pulse duration of 30 ns and beam energy up to 450 mJ was employed to form vias in 4H-SiC substrates and Lely platelets. SEM micrographs have been used to evaluate etched material quality as well as etch rate. The area surrounding the via-holes is covered by nanoparticles, which are debris from the laser ablation and are removed by chemical cleaning and agitation. The etch-rate exhibits a perfect linear behaviour versus the number of laser pulses showing the possibility of an all-laser via-hole formation. A slight tapering along the via-holes, useful for the subsequent metallization process is also observed. Finally, a defective,15 μm wide, zone is formed nearby the sidewalls.

A classical implementation of the field plate technique is the oxide ramp termination. This paper presents improvements of the breakdown voltage for both SiC JBDs and SBDs, obtained by using high-k dielectrics. A study regarding the influence of the dielectric permittivity and thickness on the off-state performances of the diodes is included. It is shown that Si3N4 is to be preferred to SiO2 for the dielectric ramp. Termination efficiencies up to 96% are reported.

The forward current was investigated in 4H-SiC p+n structures grown by sublimation epitaxy. The doping level, Nd-Na, of the n-layer was about (3-4)x1016 cm-3 and the diode area was in the range from 1x10-5 to 2x10-4 cm2. The observed current can be considered as current due to bulk recombination in the space charge region of the pn junction via deep level center or due to surface recombination. The criterion which was performed in this study to differentiate such currents was the investigation of recombination current versus perimeter/area ratio dependence. It was found that no pronounced difference in the recombination current parameters for diodes with different perimeter/area ratio was observed, i.e. current due to surface recombination was not observed for the 4H-SiC pn structures investigated.

The packaged microwave 4H SiC pin diode chips (with i-region length of 6 μm, mesa diameter of 80 μm and blocking voltage of 1000 V) were investigated. We studied the parameters of diode I−V curve (in particular, the diode resistance RS at forward current) and the processes of diode switching from forward current of 50 mA to reverse voltage of 15 V, as well as C−V curves, in the 20−700 °C temperature range. At a voltage of 300 V, the diode reverse current was 10 (180) μA when temperature was 600 (700) °C. At a forward current of 40 mA, the diode resistance first decreases smoothly as temperature is increased from 20 up to 300 °C, and then grows up. As temperature is increased from 20 up to 700 °C, the effective lifetime τeff grows from 7 up to 50 ns, while the diode capacitance (in the 0−40 V reverse voltage range) grows smoothly as temperature is increased from 20 up to 400 °C.

The electrical and low frequency noise properties of 4H-SiC p+–n–n+ junctions have been investigated at different temperatures. The forward current–voltage characteristics are described as the sum of a recombination current originating from carrier recombination on the sidewall of the circular mesa of the diodes and a diffusion volume current. In the current region where the recombination mechanism is dominant, the main noise sources are attributed to carrier recombination at the perimeter surface of the diode and to a generation-recombination noise related to a local trap level. In the current region where the diffusion current becomes important, the noise originates from mobility and diffusivity fluctuations in the space charge region of the p+–n junction. Analysis of the current and noise data allowed us to determine the density of surface states and the Hooge factor, characterizing the surface and the bulk quality of the diode. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The switching characteristics of 4Н-SiС p-i-n diodes with 6 µm long i-region were investigated in the 20÷500 °С temperature ranges. It is shown that the diode reverse current increases with temperature and does not exceed 10-7 А at temperature of 500 °С (UR = 100 V). The diode resistance rF at forward current of 40 mA decreases as temperature increases from 20 up to 500 °С. The effective minority charge carrier lifetime in the i-region (τр) was determined from the diode switching (from forward current to reverse voltage) characteristics; it was about 5 ns. As temperature increases from 20 up to 500 °С, τр increases by a factor of 3. We discuss the possibility of application of such diodes (i) in microwave switching facilities and (ii) as temperature sensors. A comparison is made between the parameters of 4Н-SiС p-i-n diodes and those of Si p-i-n diodes with comparable values of calculated blocking voltage.

The defects were investigated in p+nn+ 4H-SiC diodes by observing the forward-biasinduced light emission through the substrate. The spatial intensity distribution, the temporal evolution and the spectral content of the electroluminescence (EL) signal have been measured in order to detect, identify and understand the defect formation during forward-bias application. It was found that, exept from the dislocations inside the epilayers, mesa etching is a main cause for the formation of extended defects. To our knowledge, for the first time, reduction of mesa-etchinginduced defects is shown in this investigation.

The defects were investigated in p+nn+ 4H-SiC diodes by observing the forward-biasinduced light emission through the substrate. The spatial intensity distribution, the temporal evolution and the spectral content of the electroluminescence (EL) signal have been measured in order to detect, identify and understand the defect formation during forward-bias application. It was found that, exept from the dislocations inside the epilayers, mesa etching is a main cause for the formation of extended defects. To our knowledge, for the first time, reduction of mesa-etchinginduced defects is shown in this investigation.

The theoretical analysis of microwave characteristics of the n + p + ν n + TUNNETT diodes made of silicon carbide is carried out. The expressions for the impedance and its active and reactive components as well as expressions for the frequency range, where the negative differential resistance takes place, and the maximal frequency of oscillations are obtained for the TUNNETT diodes made of SiC. After numerical calculations, the conclusion is made that the performance potential of TUNNETTs is better than that of the other transit time devices in very high frequency range. The use of silicon carbide for the manufacture of TUNNETTs can promise better microwave parameters over the range of frequencies 100–500 GHz.

Current transport mechanisms in 4H-SiC pn diodes have been investigated by current-voltage and under-bias-photoemission experiments. In low voltages (1.9 to 2.6 Volts) current recombination dominates forward current. Moreover, carrier recombination takes place on the perimeter of the diodes. From 2.6 to 2.8 Volts a mixed conduction with recombination and diffusion components or recombination through multielectron centers in the space charge region is observed.