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The pursuit of sub‐1‐nm field‐effect transistor (FET) channels within 3D semiconducting crystals faces challenges due to diminished gate electrostatics and increased charge carrier scattering. 2D semiconductors, exemplified by transition metal dichalcogenides, provide a promising alternative. However, the non‐idealities, such as excess low‐frequency noise (LFN) in 2D FETs, present substantial hurdles to their realization and commercialization. In this study, ideal LFN characteristics in monolayer MoS2 FETs are attained by engineering the metal‐2D semiconductor contact and the subgap density of states (DOS). By probing non‐ideal contact resistance effects using CuS and Au electrodes, it is uncovered that excess contact noise in the high drain current (ID) region can be substantially reduced by forming a van der Waals junction with CuS electrodes. Furthermore, thermal annealing effectively mitigates sulfur vacancy‐induced subgap density of states (DOS), diminishing excess noise in the low ID region. Through meticulous optimization of metal‐2D semiconductor contacts and subgap DOS, alignment of 1/f noise with the pure carrier number fluctuation model is achieved, ultimately achieving the sought‐after ideal LFN behavior in monolayer MoS2 FETs. This study underscores the necessity of refining excess noise, heralding improved performance and reliability of 2D electronic devices. [ABSTRACT FROM AUTHOR]

Interface issues with organic semiconductors on metal oxide challenge realizing a high‐performance anti‐ambipolar transistor (AAT) with stable operation. The motivation behind this research delves into the intricate landscape of AATs, elucidating their envisioned applications and constituent materials. Central to the authors, discourse is the pivotal role that fluoropolymers assume, acting as a bridge uniting n‐type metal oxide semiconductors (n‐oxide) with p‐type organic semiconductors (p‐organic), thereby unveiling a hitherto concealed facet of transistor advancement. Adopting a spatially separating layer (SSL) between p‐ and n‐type semiconductors of AAT is unconventional, but this p‐organic/SSL/n‐oxide junction (pSn) AAT exhibits stable operation also 215 days after fabrication and minimal hysteresis, which is 13.67 times smaller than a conventional p‐organic/n‐oxide junction (pn) AAT. The effect of SSL is closely studied through comparisons of the performance of single‐type transistors, trap density, and carrier behavior, which define the order of 1/f at low‐frequency noise analysis. In addition, the contribution of SSL is confirmed via the channel formation mechanism of AAT investigated through a two‐dimensional (2D) finite‐element simulation. The operation stability of pSn AAT is evaluated through combined stress tests, long‐term stability tests, and transient response tests. This research proposes SSL as a new design parameter to improve the AAT. [ABSTRACT FROM AUTHOR]

Hardware neuromorphic systems are crucial for the energy‐efficient processing of massive amounts of data. Among various candidates, hafnium oxide ferroelectric tunnel junctions (FTJs) are highly promising for artificial synaptic devices. However, FTJs exhibit non‐ideal characteristics that introduce variations in synaptic weights, presenting a considerable challenge in achieving high‐performance neuromorphic systems. The primary objective of this study is to analyze the origin and impact of these variations in neuromorphic systems. The analysis reveals that the major bottleneck in achieving a high‐performance neuromorphic system is the dynamic variation, primarily caused by the intrinsic 1/f noise of the device. As the device area is reduced and the read bias (VRead) is lowered, the intrinsic noise of the FTJs increases, presenting an inherent limitation for implementing area‐ and power‐efficient neuromorphic systems. To overcome this limitation, an adaptive read‐biasing (ARB) scheme is proposed that applies a different VRead to each layer of the neuromorphic system. By exploiting the different noise sensitivities of each layer, the ARB method demonstrates significant power savings of 61.3% and a scaling effect of 91.9% compared with conventional biasing methods. These findings contribute significantly to the development of more accurate, efficient, and scalable neuromorphic systems. [ABSTRACT FROM AUTHOR]

The presence of low‐frequency noise (LFN) in amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) is of utmost concern, prompting extensive investigations into the analysis of LFN. However, prior research endeavors have tended to overlook the significance of the sub‐gap density of states (DOS) in the LFN analysis, resulting in an incomplete comprehension. To bridge this knowledge gap, the influence of sub‐gap DOS is demonstrated on LFN in Si‐doped ZnSnO (SZTO) thin‐film transistors (TFTs) under various conditions. The SZTO TFTs is intentionally subjected to positive bias stress and hot carrier stress in order to control the sub‐gap DOS and investigate how this change affects the LFN characteristics. It is revealed that the non‐uniform energetic distribution of sub‐gap DOS induces bias‐dependent excess noise in the SZTO TFTs. Additionally, self‐recovery behavior after the HCS is observed, accompanied by a commensurate reduction in 1/f noise. These empirical observations provide evidence that the conventional correlated mobility fluctuation model used to explain LFN in AOS TFTs is insufficient and underscores the critical importance of considering subgap DOS when analyzing LFN of AOS TFTs. [ABSTRACT FROM AUTHOR]

In recent years, neuromorphic computing has been rapidly developed to overcome the limitations of von Neumann architecture. In this regard, the demand for high‐performance synaptic devices with high switching speeds, low power consumption, and multilevel conductance is increasing. Among the various synaptic devices, ferroelectric tunnel junctions (FTJs) are promising candidates. While previous studies have focused on improving reliability of FTJs to enhance the synaptic behavior, low‐frequency noise (LFN) of FTJs has not been characterized and its impact on the learning accuracy in neuromorphic computing remains unknown. Herein, the LFN characteristics of FTJs fabricated on n‐ and p‐type Si along with the impact of 1/f noise on the learning accuracy of convolutional neural networks (CNNs) are investigated. The results indicate that the FTJ on p‐type Si exhibits a far lower 1/f noise than that on n‐type Si. The FTJ on p‐type Si exhibits a significantly higher learning accuracy (86.26%) than that on n‐type Si (78.70%) owing to its low‐noise properties. This study provides valuable insights into the LFN characteristics of FTJs and a solution to improve the performance of synaptic devices by significantly reducing the 1/f noise. [ABSTRACT FROM AUTHOR]

The pursuit of sub-1-nm field-effect transistor (FET) channels within 3D semiconducting crystals faces challenges due to diminished gate electrostatics and increased charge carrier scattering. 2D semiconductors, exemplified by transition metal dichalcogenides, provide a promising alternative. However, the non-idealities, such as excess low-frequency noise (LFN) in 2D FETs, present substantial hurdles to their realization and commercialization. In this study, ideal LFN characteristics in monolayer MoS 2 FETs are attained by engineering the metal-2D semiconductor contact and the subgap density of states (DOS). By probing non-ideal contact resistance effects using CuS and Au electrodes, it is uncovered that excess contact noise in the high drain current (I D ) region can be substantially reduced by forming a van der Waals junction with CuS electrodes. Furthermore, thermal annealing effectively mitigates sulfur vacancy-induced subgap density of states (DOS), diminishing excess noise in the low I D region. Through meticulous optimization of metal-2D semiconductor contacts and subgap DOS, alignment of 1/f noise with the pure carrier number fluctuation model is achieved, ultimately achieving the sought-after ideal LFN behavior in monolayer MoS 2 FETs. This study underscores the necessity of refining excess noise, heralding improved performance and reliability of 2D electronic devices., (© 2024 The Authors. Advanced Science published by Wiley‐VCH GmbH.)