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Several experimental and analytical studies are conducted to examine the transient and operation of a silicon avalanche transistor in the high-current short-pulsing mode. The operation is shown to be highly dependent on the lateral current confinement taking place in the lateral direction.

An analysis of a proposed source-follower (SF)-based buffer circuit and its performance is presented. High linearity and wide bandwidth are achieved by the use of adaptive biasing of a SF transistor to mitigate the impact of the load current of the buffer and to speed up the settling behavior. The adaptive biasing is realized by means of a low gain current domain feedback that allows simultaneous scaling of the bias currents and signal bandwidth and hence enables the realization of power-efficient buffers for circuits that are used in varying conditions, such as analog-digital converters. The theory specifies the dominant distortion mechanisms, and thus, together with a noise analysis and a discussion of the design options, enables efficient design optimization. The simulation cases support the analysis and show that the proposed buffer topology enables a buffer to be constructed that has a ~75-dB spurious-free dynamic range, for example, with ~50-MHz signal bandwidth using 0.35-[micro]m CMOS transistors. Index Terms--Buffer, local feedback, sample-land-hold (S&H) circuit, sampling, source-follower (SF), voltage follower.

A charge-domain sampling technique for realization of mixed-mode finite-impulse response (FIR) filters is presented. The method is based on weighting signal current samples integrated into a sampling capacitor with a set of parallel digitally controlled current-mode switches each carrying a unit current element. The fine achievable resolution and digital controllability of the filter tap coefficients allows realization of advanced programmable FIR filtering functions embedded into high-frequency signal sampling. Circuit-level simulation results of an example 50-MHz IF-sampler with a built-in 22-tap complex bandpass [sinc.sup.3) FIR function in 0.35-/[micro]m CMOS are shown, demonstrating the feasibility of the presented method. Index Terms--Charge domain, complex filters, finite-impulse response (FIR) filters, radio receivers, subsampling.

An integrated receiver channel for a pulsed time-of-flight laser range finder is presented. The receiver operates in a wide dynamic range without gain control. This is achieved by converting the received unipolar pulse to a bipolar waveform already after the optical detector before the signal is fed to amplifier blocks. Thus the nonlinearities of the amplifiers have the minimum effect on the timing point, which is located in the zero crossing of the bipolar pulse. A parallel resonant circuit is used to shape the pulse in the input of the channel, which consists of a cascade of limiting voltage amplifiers followed by a comparator. The measurements show that the receiver has a walk error of 74 ps in the dynamic range of 1:1280. This corresponds to 11 mm in distance. The minimum usable input signal is limited by the noise of the receiver and equals 1.9 [micro]A. Index Terms--Comparator, laser range finding, optical distance measurement, timing discrimination.

The effect of superfast avalanche switching in a GaAs bipolar-junction transistor (BJT) structure is examined. The findings suggest that homogeneous and simultaneous high-rate carrier generation across the entire thickness of the blocking region, cause superfast transient in GaAs BJT.

A low-voltage low-power signal processing chip for electrocardiogram measurements has been designed and manufactured. The circuit includes a continuous time, offset-compensated preamplifier with an amplification of 40 dB, an eighth-order Butterworth switched-opamp switched-capacitor (SO-SC) filter with a passband of 8-30 Hz, a 32-kHz crystal oscillator, an SO-SC postamplifier, and a bias circuit. The whole circuit operates with supply voltages from 1.0 to 1.8 V and the measured average current consumption is only about 3 [micro]A. The circuit is therefore very suitable for portable applications such as heart rate detectors. Index Terms--Heart-rate detector, low-voltage low-power biomedical devices, switched-capacitor (SC) filters, switched opamps (SO).

A method for digital delta-sigma modulator design for fractional-N frequency synthesis is presented in this paper. The design method is based on the modulator periodical behavior analysis. The modulator is designed to maintain a constant output signal sequence length which can be controlled for all input dc levels. As a result, the quantization noise power is spread over a known, arbitrarily large number of tones within the Nyquist bandwidth. Therefore, the quantization noise power never concentrates into a few dominant spurious tones. The sequence length is controlled by applying predefined initial conditions and scaling modulator buses. Consequently, the spurious-free range can be controlled as a function of the bus width. Known modulator sequence length defines the time required for full modulator and synthesizer characterization. Index Terms--Delta-sigma modulation (DSM), digital circuits, frequency synthesizers, limit cycles, phase noise.

A charge-domain quadrature sampling circuit realization in 0.35[micro]m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in antialiasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply. Index Terms--Charge domain, complex filters, finite-impulse response (FIR) filters, quadrature downconversion, radio receivers, subsampling.

This paper reviews several techniques used to reduce the in-band phase noise contribution of [DELTA][SIGMA] fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a [DELTA][SIGMA] fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-/[micro]m SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state-of-the-art. Index Terms--Bluetooth, Delta-Sigma, frequency modulation (FM), frequency-shift keying (FSK), Gausian frequency shift keying (GFSK), GMSK minimum shift keying (MSK), general packet radio service (GPRS), global system for mobile communications (GSM), multimode, radio, satellite, Sigma-Delta, wireless.

This paper studies a group of methods designed to speed-up the frequency step response of integer-N phase-locked loops (PLLs). The methods are based on current signals connected to the loop filter. Optimal speed-up waveforms are found mathematically using a linear PLL model. The paper also discusses problems associated with this theoretical waveform and introduces a considerably simpler waveform based on the use of two current pulses. This method uses excess output frequency to quickly cancel the accumulated phase error. In order to accelerate the decay of the phase error, the PLL is first overdriven at the beginning of the frequency transition with an external charge pulse to the loop filter. As the phase error goes rapidly to zero, the frequency error is also reduced to zero by another charge pulse. The theory presented here is verified by measurements using a practical RF synthesizer. Index Terms--Phase-locked loop (PLL), integer-N, fast frequency hopping.

This paper proposes a new frequency synthesizer architecture which uses a combination of known techniques. The architecture is evaluated by simulation and shown to reduce spurious content of existing fractional-N synthesizers. It also allows arbitrarily small channel spacing with existing fractional-N synthesizers. Index Terms--Bluetooth, FSK, GFSK, GMSK, GSM GPRS, MSK, multi-mode FM.

A particular transistor switching at extreme currents is studied under condition. It is specifically shown that fundamental parameters of the semiconductor material such as the detailed dependencies of the electron and hole velocities and ionization rates on the electric field determine the possibility for achieving high current switching.