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Digital active gate driving has been shown to effectively manage the switching performance for power devices with the adjustable driving waveforms. However, most of the studies are based on a dedicated test circuit rather than a practical inverter with the sinusoidal output current. In fact, it is the dependency on the load current that makes the design of the gate driving profiles a critical issue. To investigate the digital active gate driver in an inverter application, this paper has applied optimal patterns adapting to time-varying output load current. Prior to the search of optimal patterns, the proper design framework is discussed with three frameworks of different time resolutions. With the proper resolution determined for patterns, multiple optimizations are carried out for different current conditions. In this way, the search for optimal patterns can be completed in an efficient time. Next, a look-up table of optimal switching pattern in correspondence with each certain load current condition was built in advance. According to the output load current, the optimal pattern is selected based on the look-up table. Compared to the conventional constant driving waveform, the power loss has been reduced by 7% with a full optimal look-up table applied.

A fully integrated load adaptive digital gate driver is proposed for high-speed and dependable SiC applications. It breaks the trade-off between surge/ringing and switching loss over a wide load range of $0 \sim 8\mathrm{A}$ by selecting the gate patterns stored in 8ch 1.5 kb LUT. Proposed time resolution expansion technique enhance them by more than 31% and reduce LUT size by 1/12. The integrated 500 ksps SAR ADC with steady sampling and automatic VDD selection schemes senses not only the load current, but also the surge and the short circuit for functional safety

The emitter resistance (R E ), the junction temperature (T J ), the collector current (I C ), and the threshold voltage (V TH ) of power devices are key parameters that determine the reliability of power devices. Adding dedicated sensors to measure the key parameters, however, will increase the cost of the power converters. To solve the problem, power device degradation estimation methods by the machine learning of gate waveforms are proposed. Two methods are shown in this paper. First, in order to detect the bond wire lift-off of power devices, the estimation of the number of the connected bond wires using the linear regression of two feature points extracted from the gate waveforms of a SiC MOSFET is shown using SPICE simulations. Then, in order to detect the power device degradation, the estimation of R E, T J , I C , and V TH using the convolutional neural network (CNN) with the gate waveforms of an IGBT for input is shown using both simulations and measurements.

An active gate driving is effective to solve the trade-off between the switching loss and the current/voltage overshoot of power transistors. The test cost in the conventional digital gate drivers with four variables, however, is high, because more than 2000 measurements are required to find an optimum gate driving vector out of 644 (~1.7 x 107) combinations [1]. To minimize the test cost, a stop-and-go gate drive with only one variable is proposed. The switching loss and the current/voltage overshoot in turn-on/off state of IGBT of the conventional gate drive [1] and the proposed stop-and-go gate drive are measured by using a 6-bit programmable digital gate driver IC across nine conditions including different load currents (20 A, 50 A, and 80 A) and temperatures (25 °C, 75 °C, and 125 °C), and they are compared. The performance degradation of the switching loss and the current/voltage overshoot in the proposed stop-and-go gate drive over the conventional gate drive with four variables [1] is less than 8 % and 25 % across the nine conditions in turn-on/off state respectively.

This paper proposes and evaluates an active gate control method of switching waveform design with digital gate drivers for a practical full-bridge inverter equipped with additional dc-link capacitors. The full-bridge inverter employs 1700-V, 150-A IGBT power modules and has a practical circuit layout with additional capacitors. The experimental system has a capability of optimizing driving patterns for shaping the designed switching waveform. In experimental verification, active gate control can suppress the surge voltage from 70% to 10% with 30% lower switching loss in three different circuit layout of the proposed practical 50-kVA full-bridge inverter. As a result, this paper reveals that active gate control achieves reduction in effect of stray inductance and increases a freedom of the circuit layout in power converters.

A digital gate driver is effective to solve the trade-off between the switching loss and the current/voltage overshoot of power transistors. A load current and temperature dependent optimization of the gate driving vectors for the digital gate drivers, however, is required [13], because an optimum vector at a particular load current and temperature does not often work at different conditions. When sensors for the load current and/or temperature are not available, the digital gate drivers are not useful under load current and temperature variations. To solve the problem, robust gate driving vectors to load current and temperature variations for the digital gate drivers are proposed. To compare a conventional single-step gate drive and the proposed robust gate driving vectors, the switching loss and the current/voltage overshoot in turn-on/off state of IGBT are measured by using a 6-bit programmable digital gate driver IC across nine conditions including different load currents (20 A, 50 A, and 80 A) and temperatures (25 °C, 75 °C, and 125 °C). The performance of the switching loss and the current/voltage overshoot of the proposed robust vectors is improved by 2% to 11 % and 16 % to 29 % across the nine conditions in turn-on/off state, respectively, which indicates that the proposed robust vectors requiring no current and temperature sensors are a useful method for the digital gate drivers.

Digital active gate drive enables the adjustable driving level in a switching transient for power devices. In this way, it is able to manage switching performance. However, to apply active gate drive in an inverter circuit, the sinusoidal output current turns out a critical problem for the design of driving profile because of its dependency on the load current. This paper aims to validate the feasibility of the digital active gate drive circuit using optimal patterns to adapt to sinusoidal output current of an inverter circuit. Firstly, a look-up table of optimal switching pattern under a certain load current condition was built in advance. It is noted that in the previous work, the online optimization system for finding the optimal pattern has been proposed and it is able to complete the searching of optimal switching pattern in an efficient time. Next, the output current of an inverter has been regulated to a sinusoidal waveform. Based on the output current, the corresponding optimal patterns are referred from the look-up table. Compared to conventional constant driving waveform, the power loss has been successfully reduced by 7% with the full optimal look-up table applied.

Active gate driving techniques using fully digital circuits and ICs have been actively investigated in the past half-decade. It has been reported that they contribute to improve loss and overshoot voltage and current, simultaneously during switching transients. However, a major concern of the digital active gate driver is an increase in the number of input signals for a practical implementation. This paper presents a verification of a digital gate driver IC with variable 63-level drivability controlled by serial four-bit input signals to decrease the implementation size and cost. Experimental results in a half-bridge converter using Si-IGBT module prove that the proposed gate driver IC realizes the active gate control effectively as the same with the conventional IC with parallel inputs despite the reduced number of the input signals. It is demonstrated that the developed digital gate driver circuit contributes to reduce the number of the input signals and digital isolators by one-thirds, and footprint of the PCB by 20% compared with the conventional gate driver IC with parallel 12-bit signal inputs.

A 500-Mbps digital isolator with the isolation voltage more than 1kV is described, which is the fastest high-voltage isolator ever reported. The high-speed feature is achieved by a newly proposed Counter-Pulse Immune Receiver (CPIR) scheme based on a cross-coupled Schmitt-trigger circuit. The isolator is manufactured in a widely-used high-voltage 0.18-μm CMOS technology and thus can be integrated with smart digital driver circuits for power electronics.

A Convolutional Neural Network (CNN) is applied to estimate the emitter resistance (R E ), the junction temperature (T J ), the collector current (I C ), and the threshold voltage (V TH ) of power devices just by monitoring the gate drive waveforms. R E , T J and I C are essential parameters for power device reliability. By using the detailed circuit simulation results for IGBT, it is shown that the above-mentioned four parameters can be estimated with the success rate more than 93% by the proposed AI-based approach for the first time. The measurement results also show that R E and I C are successfully estimated with the success rate >99%. The discussions are made on the success rate change depending on the resolution and the sampling rate of an A/D converter and the convolution filter kernel size.

A gate driving for power devices is the key technology to further improve switching characteristics of power converter circuit. With the help of digital gate driver IC, the enhancement on switching behavior of power devices can be achieved even under high-speed switching. In this paper, an optimization system to find the switching pattern of active gate drive control is proposed for an inverter circuit. A high-speed optimization system is built up to search the advantageous switching pattern which is able to reduce total switching loss of two power devices in the inverter circuit and constrain overshoot voltage in the meanwhile. The proposed online optimization is carried out and demonstrates its feasibility for the investigated inverter circuit, rated at 500 V with digital active gate drive.

This paper proposes an active gate control method for switching waveform shaping irrespective of circuit stray inductance and an evaluating system based on a practical full-bridge inverter equipped with digital gate drivers. The main circuit of the proposed system has 1700-V, 150-A IGBT power modules in a practical circuit layout resulting in large stray inductances. The proposed system has a capability of optimizing driving patterns for shaping the designed switching waveform. In experimental verification, active gate control can suppress the surge voltage from higher than 60% to 6% with a fast switching speed in three different circuit layout of the proposed practical 50-kVA full-bridge inverter. As a result, this paper reveals that active gate control achieves reduction in effect of stray inductance and increases a freedom of the circuit layout in power converters.

The emerging trend of internet of things (IoT) and artificial intelligence (AI) technologies will bring about a major change in power electronics and create a new generation of the power electronics (Power Electronics 2.0). To enable the IoT- and Al-assisted Power Electronics 2.0, the integration of the sensors, the programmable hardware, and VLSIs for the controller into the power devices/modules is very important. In this paper, a 6-bit programmable gate driver IC with automatic optimization of gate driving waveform for IGBT is presented as the first step toward Power Electronics 2.0. In the proposed gate driver, the 6-bit gate control signals with four 160-ns time steps are globally optimized using a simulated annealing algorithm, reducing the collector current overshoot by 37% and the switching loss by 47% at the double pulse test of 300V, 50A IGBT. The gate driver is also applied to a half-bridge inverter, where the gate driving waveform is changed depending on the load current.

The requirements for peripheral circuits of power converters are becoming restrictive due to the enhancement of Si power devices and the practical use of SiC and GaN devices. In the design of recent converters with high-speed switching, we must consider the stray inductances and capacitances in the device package and the gate drive circuit in addition to those in the main circuit of the power converter. In these situations, the gate driving technique is a key technology to enhance the high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. However, most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, we have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable full-digital 12-bit and the clock signals. In this study, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. It is verified that the proposed active gate control can effectively improve the trade-off relationship between the surge voltage and switching loss of the PWM half-bridge inverter circuit.

Advanced IGBTs need to be shut off when a short circuit occurs within less than 0.5μs as the current density of IGBTs increases. In this paper, a circuit design and the measurement results are described for an IC chip which enables the short-circuit detection within 20-ns. The circuit detects the short-circuit condition by checking the existence of a plateau in a gate drive waveform. The proposed scheme can provide much higher variation-tolerance compared with the conventional scheme by introducing adaptive threshold-time determination. This adaptive feature is realized for the first time using a novel analog delay multiplier circuit. The chip was fabricated in 0.18-μm TSMC high-voltage CMOS technology. The measurements are carried out and the short-circuit detection operation is successfully verified even though the gate driving waveform slope is varied 10 times. The slope variation is cased possibly due to the variation of the gate drive current and/or the gate capacitance (CGE+CGC). Added to the benefits described above, it does not need any special off-chip component such as an IGBT with a Kelvin emitter, a parasitic inductor, and an inherently slow current monitor. Thus, it can be applicable to a wide range of power circuits with advanced IGBTs.

A general-purpose clocked gate driver (CGD) IC to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with 0.18µm BCD process has 63 PMOS and 63 NMOS driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 25-MHz clock (= 40-ns time step control). In the 500-V switching measurements, the proposed CGD reduces the IC overshoot by 25% and 41% and the energy loss by 38% and 55% for Si-IGBT and SiC-MOSFET, respectively.