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In the paper, we consider the urgent need to create highly efficient hardware accelerators for machine learning algorithms, including convolutional and deep neural networks (CNN and DNNS), for associative memory models, clustering, and pattern recognition. We show a brief overview of our related works the advantages of the equivalent models (EM) for describing and designing bio-inspired systems. The capacity of NN on the basis of EM and of its modifications is in several times quantity of neurons. Such neural paradigms are very perspective for processing, clustering, recognition, storing large size, strongly correlated, highly noised images and creating of uncontrolled learning machine. And since the basic operational functional nodes of EM are such vector-matrix or matrix-tensor procedures with continuous-logical operations as: normalized vector operations “equivalence”, “nonequivalence”, and etc. , we consider in this paper new conceptual approaches to the design of full-scale arrays of such neuron-equivalentors (NEs) with extended functionality, including different activation functions. Our approach is based on the use of analog and mixed (with special coding) methods for implementing the required operations, building NEs (with number of synapsis from 8 up to 128 and more) and their base cells, nodes based on photosensitive elements and CMOS current mirrors. Simulation results show that the efficiency of NEs relative to the energy intensity is estimated at a value of not less than 1012 an. op. / sec on W and can be increased. The results confirm the correctness of the concept and the possibility of creating NE and MIMO structures on their basis.

A The article considers the peculiarities of the application of isomorphic matrix representations for modeling the protocol of matching secret keys-permutations of significant dimension. The situation is considered when for cryptographic transformations of blocks with a length of 256 * 256 bytes, presented in the form of a matrix of a black-and-white image, it is necessary to rearrange all bytes in accordance with the matrix keys. To generate a basic matrix key and the appearance of the components KeyA and KeyB in the format of two black and white images, a software module using engineering mathematical software Mathcad is proposed. Simulations are performed, for example, with sets of fixed matrix representations. The essence of the protocol of coordination of the main matrix of permutations by the parties is considered. Also shown are software modules in Mathcad for accelerated methods that display the procedure of iterative permutations in a permutation matrix isomorphic to the elevation of the permutation matrix to the desired degree with a certain side, corresponding to specific bits of bits or other code representations of selected random numbers. It is demonstrated that the parties receive new permutation matrices after the first step of the protocol, those sent to the other party, and the identical new permutation matrices received by the parties after the second step of the protocol, ie the secret permutation matrix. Similar qualitative cryptographic transformations have been confirmed using the proposed representations of the permutation matrix based on the results of modeling matrix affine-permutation ciphers and multi-step matrix affine-permutation ciphers for different cases when the components of affine transformations are first executed in different sequences. , and then permutation using the permutation matrix, or vice versa. The model experiments performed in the study demonstrated the adequacy of the functioning of the models proposed by the protocol and methods of generating a permutation matrix and demonstrated their advantages.

In this chapter, the authors consider the need and relevance of cryptographic transformation of images and video files that are transmitted from unmanned aircraft, airborne robots. The authors propose and consider new multifunctional matrix-algebraic models of cryptographic image transformations, the variety of matrix models, including block parametrical and matrix affine permutation ciphers. The authors show the advantages of the cryptographic models, such as adaptability to various formats, multi-functionality, ease of implementation on matrix parallel structures, interchangeability of iterative procedures and matrix exponentiation modulo, ease of selection, and control of cryptographic transformation parameters. The simulation results of the proposed algorithms and procedures for the direct and inverse transformation of images with the aim of masking them during transmission are demonstrated and discussed in this chapter. The authors evaluate the effectiveness and implementation reliability of matrix-algebraic models of cryptographic image transformations.

A new iterative process for sorting array of signals, which differs from the known structures by uniformity and versatility, and allows direct and inverse sorting of analog or digital signal arrays was proposed in this paper. Simple relational nodes are basic elements of the proposed sorting structures. Such elements can be implemented on a different element basis, for example, on devices of selecting a maximum or minimum of two analog or digital signals, which can be implemented on CMOS current mirrors and carry out the continuous logic limited difference function. The homogeneous sorting structure on such elements implementation, consisting of two layers and a multichannel sampling and holding device was offered. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, and are sorted by five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, that corresponds to the selected rank. Technical parameters of such relational preprocessor were evaluated. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputsoutputs. Such sorting nodes have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes possible to significantly simplify its design and increase the functional capabilities of such processor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 operations per second per watt, which corresponds to the best technical solutions. In the work we show, that after sorting or comparative analysis of signals by levels, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We show that using this approach and the method of processing we can significantly expands the set of operations and functions for image filtering, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic executable instruction-functions of the processors, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable selecting function or set of functions, including the selecting the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that in the case of using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

In this paper we proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. We proposed the structure of the processor based on the node that sorts the array of processed signals. Let us show the variety of the sorting node, which can be executed both iterative and pipeline–type, implementation of homogeneous sorting structure, consisting of two layers of base cells and a multichannel sampling and holding device and show that for a large number of operations and functions performed on image processing and filtering, it is necessary to sort by the signal level in the selected image window. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes it possible to significantly simplify its design and increase the functional capabilities of such processor. We evaluated the technical parameters of such a relational preprocessor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type, which simplify the complexity of the nodes by an order of magnitude, ensuring their uniformity, regularity and simplicity of scaling. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 op / s • W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined the set of executed command functions by such a processor based on the sorting node, show how it can be used to separate the rank from the array of signals and analyze the new approach for the programmable selection of the required rank or the difference between the signal ranks. The use of difference-rank decomposition allows to significantly expanding the transformations range, performed over the signals of the current fragment of the processed image. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

In this paper, we proposed a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented on CMOS current mirrors and carry out the limited difference function of continuous logic. We offered implementation of homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluated the technical parameters of such a relational preprocessor. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs. The paper considers results of design and modeling of CL BC based on current mirrors (CM) for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The inclusion of an iterative node for sorting signals into a modified nonlinear IP structure makes it possible to significantly simplify its design and increase the functional capabilities of such processor. The simulation results confirm the proposed approaches to the design of sorting nodes of analog signals of the iterative type, which simplify the complexity of the nodes by an order of magnitude, ensuring their uniformity, regularity and simplicity of scaling. The power consumption of the processors does not exceed 2mW, the response and processing times are 10μs and can be less by an order of magnitude, the supply voltage is 1.8÷3.3V, and the operating currents are optimally in the range of 10÷20μA. The energy efficiency of the proposed preprocessor with the iterative sorting node is 25x109 op / s•W, which corresponds to the best technical solutions. In the work we are shown, that after sorting or comparative analysis of signals by levels of selected window of image, a promising opportunity appears to implement image processors with enhanced functionality using the new method of weighting-selecting rank differences of signals. The essence of the method is that by composing the differences of the signals ordered by rank and the upper level of their range, we can simultaneously form several resulting output signals, choosing the necessary difference signals from their set according to the control commands and weighing them additionally before the summation. We are shown that using this approach and the method of processing the current window signals significantly expands the set of operations and functions for filtering images, simplifying hardware implementation of IP, especially for analog and mixed technologies. We determined set of basic possible executable instruction-functions by processors based on such a proposed method, presenting the simulation results in Mathcad, PSpice OrCad and other environments. We discussed the comparative evaluation of various modifications and options for implementing processor. We analyzed the new approach for the programmable choice of its function or set of functions, including the choice of the required differences between the ranks of signals and their weights. We show the results of design and modeling the proposed new FPGA-implementations of MIP. Simulation results show that processing time in such circuits does not exceed 25 nanoseconds. Circuits are simple, have low supply voltage (2.5 V), low power consumption (50mW), digital accuracy. Calculations show that when using an Altera FPGA chip EP3C16F484 Cyclone III family, it is possible to implement MIP with register memory for image size of 64*64 and window 3*3 in the one chip. For the chip for 2.5V and clock frequency 200MHz the power consumption will be at the level of 200mW, and the calculation time for pixel of filters will be at the level of 25ns.

First, in the introduction, we will show the urgent need to create neuron-calculators (NCs) for the normalized equivalence of two matrix arrays for self-learning equivalently-convolutional neural networks (SLE_CNNs), video processors for parallel image processing with enhanced functionality. Consider promising areas of application of such single and multichannel neuron-calculators as high-precision, high-speed and high-performance accelerators for hardware systems and architectures for recognition, classification, image categorization, in particular for 2D-image space-invariant associative memory structures, SLE_CNNs based on the equivalence paradigm. Next, we will consider and analyze the theoretical foundations, the mathematical apparatus of matrix and continuous logic, and their basic operations, show their functional completeness, evaluate their advantages and prospects for application in the design of biologically inspired devices and systems for processing and analyzing signal arrays. We will show that some functions of continuous logic, including operations of normalized equivalence of vector and matrix signals, operation of the bounded difference of continuous logic, are the powerful basis for designing advanced accelerator calculators, microcells for hybrid (mixed) analog-to-digital transformations, comparisons and calculations of characteristics. Next, we will consider in more detail the design and simulation aspects of such digital neuron-calculators for the normalized equivalence of two matrix arrays based on FPGA, including their various modifications, depending on the dimension and the number of compared arrays. We will propose our approach for calculation of the normalized equivalence functions comparing current fragments of images and filters with dimensions 3×3, 7×7, 15×15, and others. The project is executed on FPGA ALTERA MAXII. The simulation was done with Intel Quartus Prime 17 and showed that in a single chip it is possible to place four parallel working neuron calculators processing 4 filters with a size of 15×15. The approximate processing time is less than 5μs. Power consumption is 50mW for supply voltage of 2.5V and clock frequency equals to 50MHz. We will also consider modifications that improve performance for different filter size. We show the results of modeling the proposed new implementations of NCs, we estimates and compare them.

In this paper, we propose a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes for analogue signals from sensor devices and cameras. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented, in one of the variants, on CMOS current mirrors and carry out the function of continuous logic limited difference. We offer optoelectronic implementation of such basic relational element and a homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluate the technical parameters of such a relational preprocessor for nonlinear signal processing in image processors, sorting networks, multichannel parallel type sensor, processing, and encoding systems. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs, but can be improved by selecting other transistors and some modifications of the circuits. Such mixed analog processor is modeled in PSpice OrCad. The paper considers results of design and modeling of CL BC based on photosensitive cells with an extended electronic circuit and current mirrors (CM) with functions of preliminary subsequent analogue processing for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such BCs and sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. We consider CL BC for methods of selection and rank preprocessing. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of iterative sorting nodes extends the range of functions performed by the IPs. Examples of image processing with proposed preprocessor are simulated in MathCad and show the field of application of such coprocessors and new prospects for realization of linear and matrix photo-electronic structures with matrix operands. The essential difference is that the structure is iterative and allows to significantly reducing hardware costs in comparison with other hardware implementations of sorting networks. We discuss some aspects of possible rules and principles of learning and programmable configuration for the required function, relational work, and the implementation of hardware blocks for modifying such processors.

The paper considers results of design and simulation of continuously logical cells (CLC) based on current mirrors (CM) with functions of preliminary analogue processing for image intensity transformation and coding for construction of mixed image processors (IP) and neural networks (NN). For such IP and NN with vector or matrix parallel inputsoutputs, it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such CLC has a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of CLC variants for photocurrents transformation and coding and their various possible implementations and simulations. The basic element of such cells is a scheme that implements the operation of a bounded difference of continuous logic. Using a set of such circuits implemented on traditional CMOS technology, we consider generalized decomposition and other methods for designing cells for nonlinear conversion of the photocurrent intensity, which makes it easy to realize the required nonlinear conversion function. Selection of the appropriate parameters, which can be specified as constructive constants or as parameters for external control, allows changing type of synthesized functions. We also consider the applications of such parallel matrix arrays for the creation of advanced IP and NN. We show the need for various types of converting and coding the photocurrents intensity in such parallel systems and sensory devices, especially for the implementation of various types of activation functions in the hardware implementations of neural networks. Such cells consist of several dozen CMOS transistors, have low power supply voltage (1.8 ÷ 3.3V), the range of an input photocurrent is 0.1÷24μA, the transformation time is less than 1 μs, low power consumption (microwatts). We also consider the cells for ADC after the intensity conversion. Each channel consists of several digital-analog cells (DC). The amount of DC is not exclusive to the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC and SHD, and it has only 35 CMOS transistors. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. The ADCs with 6-8 bit binary or Gray codes have good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 10MHz and more). In such ADCs, easily parallel code can be realized. The circuits and the simulation results of their design with OrCAD are shown. The CLC and ADC on current mirrors open new prospects for realization of linear and matrix IP and NN with MIMO-operands.

In the paper, we consider the urgent need to create highly efficient hardware accelerators for machine learning algorithms, including convolutional and deep neural networks (CNN and DNNS), for associative memory models, clustering, and pattern recognition. These algorithms usually include a large number of multiply-accumulate (and the like) operations. We show a brief overview of our related works the advantages of the equivalent models (EM) for describing and designing neural networks and recognizing bio-inspired systems. The capacity of NN on the basis of EM and of its modifications, including auto-and hetero-associative memories for 2D images, is in several times quantity of neurons. Such neuroparadigms are very perspective for processing, clustering, recognition, storing large size and strongly correlated and highly noised images. They are also very promising for solving the problem of creating machine uncontrolled learning. And since the basic operational functional nodes of EM are such vector-matrix or matrix-tensor procedures with continuous-logical operations as: normalized vector operations "equivalence", "nonequivalence", "autoequivalence", "auto-nonequivalence", we consider in this paper new conceptual approaches to the design of full-scale arrays of such neuron-equivalentors (NEs) with extended functionality, including different activation functions. Our approach is based on the use of analog and mixed (with special coding) methods for implementing the required operations, building NEs (with number of synapsis from 8 up to 128 and more) and their base cells, nodes based on photosensitive elements and CMOS current mirrors. We show the results of modeling the proposed new modularscalable implementations of NEs, we estimates and compare them. Simulation results show that processing time in such circuits does not exceed units of micro seconds, and for some variants 50-100 nanoseconds. Circuits are simple, have low supply voltage (1.5 – 3.3 V), low power consumption (milliwatts), low levels of input signals (microwatts), integrated construction, satisfy the problem of interconnections and cascading. Signals at the output of such neurons can be both digital and analog, or hybrid, and also with two complement outputs. They realize principle of dualism which gives a number of advantages of such complement dual NEs.

The biologically-motivated self-learning equivalence-convolutional recurrent-multilayer neural structures (BLM_SL_EC_RMNS) for fragments images clustering and recognition will be discussed. We shall consider these neural structures and their spatial-invariant equivalental models (SIEMs) based on proposed equivalent two-dimensional functions of image similarity and the corresponding matrix-matrix (or tensor) procedures using as basic operations of continuous logic and nonlinear processing. These SIEMs can simply describe the signals processing during the all training and recognition stages and they are suitable for unipolar-coding multilevel signals. The clustering efficiency in such models and their implementation depends on the discriminant properties of neural elements of hidden layers. Therefore, the main models and architecture parameters and characteristics depends on the applied types of non-linear processing and function used for image comparison or for adaptive-equivalent weighing of input patterns. We show that these SL_EC_RMNSs have several advantages, such as the self-study and self-identification of features and signs of the similarity of fragments, ability to clustering and recognize of image fragments with best efficiency and strong mutual correlation. The proposed combined with learning-recognition clustering method of fragments with regard to their structural features is suitable not only for binary, but also color images and combines self-learning and the formation of weight clustered matrix-patterns. Its model is constructed and designed on the basis of recursively continuous logic and nonlinear processing algorithms and to k-average method or method the winner takes all (WTA). The experimental results confirmed that fragments with a large numbers of elements may be clustered. For the first time the possibility of generalization of these models for space invariant case is shown. The experiment for an images of different dimensions (a reference array) and fragments with diferent dimensions for clustering is carried out. The experiments, using the software environment Mathcad showed that the proposed method is universal, has a significant convergence, the small number of iterations is easily, displayed on the matrix structure, and confirmed its prospects. Thus, to understand the mechanisms of self-learning equivalence-convolutional clustering, accompanying her to the competitive processes in neurons, and the neural auto-encoding-decoding and recognition principles with the use of self-learning cluster patterns is very important which used the algorithm and the principles of non-linear processing of two-dimensional spatial functions of images comparison. The experimental results show that such models can be successfully used for auto- and hetero-associative recognition. Also they can be used to explain some mechanisms, known as "the reinforcementinhibition concept". Also we demonstrate a real model experiments, which confirm that the nonlinear processing by equivalent function allow to determine the neuron-winners and customize the weight matrix. At the end of the report, we will show how to use the obtained results and to propose new more efficient hardware architecture of SL_EC_RMNS based on matrix-tensor multipliers. Also we estimate the parameters and performance of such architectures.

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the maximum input current is 4μA. Such simple structure of linear array of ADCs with low power consumption and supply voltage 3.3V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40÷50 MHz, and can be increased up to 10 times) and accuracy characteristics are show. The SMC ADCs based on CL BC and CM opens new prospects for realization of linear and matrix IP and photo-electronic structures with matrix operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers.

Today real-time studying and tracking of movement dynamics of various biological objects is important and widely researched. Features of objects, conditions of their visualization and model parameters strongly influence the choice of optimal methods and algorithms for a specific task. Therefore, to automate the processes of adaptation of recognition tracking algorithms, several Labview project trackers are considered in the article. Projects allow changing templates for training and retraining the system quickly. They adapt to the speed of objects and statistical characteristics of noise in images. New functions of comparison of images or their features, descriptors and pre-processing methods will be discussed. The experiments carried out to test the trackers on real video files will be presented and analyzed.

The structures of optical neural nets (NN) based on new matrix-tensor equivalental models (MTEMs) and algorithms are described in this article. MTE models are neuroparadigm of non-iterative type, which is a generalization of Hopfield and Hamming networks. The adaptive multi-layer networks, auto-associative and hetero-associative memory of 2-D images of high order can be built on the basis of MTEMs. The capacity of such networks in comparison with capacity of Hopfield networks is increased (including capacity for greatly correlated images). The results of modeling show that the number of neurons in neural network MTEMs is 10–20 thousand and more. The problems of training of such networks, different modifications, including networks with double adaptive-equivalental auto-weighing of weights, organization of computing process in different modes of network are discussed. The basic components of networks: matrix-tensor “equivalentors” and variants of their realization on the basis of liquid-crystal structures and optical multipliers with spatial and time integration are considered. The efficiency of proposed optical neural networks on the basis of MTEMs is evaluated for both variants on the level of 109 connections per second. Modified optical connections are realized as liquid-crystal television screens.

We have proposed and discussed optical pattern recognition algorithms for object tracking based on nonlinear equivalent models and subtraction of frames. Experimental results of suggested algorithms in Mathcad and LabVIEW are shown. Application of equivalent functions and difference of frames gives good results for recognition and tracking moving objects.

We have proposed a design and simulation of hardware realizations of smart multifunctional continuous logic devices (SMCLD) as advanced basic cells of the sensor systems with MIMO- structure for images processing and interconnection. The SMCLD realize function of two-valued, multi-valued and continuous logics with current inputs and current outputs. Such advanced basic cells realize function nonlinear time-pulse transformation, analog-to-digital converters and neural logic. We showed advantages of such elements. It’s have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. The conception of construction of SMCLD consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 50÷70 transistors, 1 PD and 1 LED makes the offered circuits quite compact. The simulation results of NOT, MIN, MAX, equivalence (EQ), normalize summation, averaging and other functions, that implemented SMCLD, showed that the level of logical variables can change from 0.1μA to 10μA for low-power consumption variants. The SMCLD have low power consumption

In the paper, we show that the nonlinear spatial non-linear equivalency functions on the basis of continuous logic equivalence (nonequivalence) operations have better discriminatory properties for comparing images. Further, using the equivalent model of multiport neural networks and associative memory, (including matrix-matrix and matrix-tensor with adaptive-weighted correlation, multi-port neural-net auto-associative and hetero-associative memory (MP NN AAM and HAM ) and the proposed architecture based on them, we show how we can modify these models and architectures for space-invariant associative recognition and clustering (high performance parallel clustering processing) images. We consider possible implementations of 2D image classifiers, devices for partitioning image fragments into clusters and their architectures. The main base unit of such architectures is a matrix-matrix or matrix-tensor equivalentor, which can be implemented on the basis of two traditional correlators. We show that the classifiers based on the equivalency paradigm and optoelectronic architectures with space-time integration and parallel-serial 2D images processing have advantages such as increased memory capacity (more than ten times of the number of neurons!), High performance in different modes . We present the results of associative significant dimension (128x128, 610x340) image recognition - renewal modeling. It will be shown that these models are capable to recognize images with a significant percentage (20- 30%) damaged pixels. The experimental results show that such models can be successfully used for auto-and heteroassociative pattern recognition. We show simulation results of using these modifications for clustering and learning models and algorithms for cluster analysis of specific images and divide them into categories of the array. Show example of a cluster division of image fragments, letters and graphics for clusters with simultaneous formation of the outputweighted spatial allocated images for each cluster. Show results of other of modeling experiments with images of large dimension, such as clustering fragments (blocks 7x 7, 3x3, 15x15 and other sizes), 610x340 elements images into 8 clusters. We show that it is the use of nonlinear processing and nonlinear functions improves the quality of classification and image recognition. We offer criteria for the quality evaluation of patterns clustering with such MP NN AAM. It is shown that time of learning in the proposed structures of multi-port neural net classifier / categorizer-clustering (MP NN C) on the basis of equivalency paradigm, due to their multi-port, decreases by orders and can be, in some cases, just a few epochs. Other experimental data is also shown.

We consider design and modeling of hardware realizations of reconfigurable multifunctional continuous logic devices (R MCL D) as advanced components of the next generation high-performance MIMO-systems for the processing and interconnection. The R MCL D realize function of two-valued and continuous logics with current inputs and current outputs on the basis of CMOS current mirrors and circuits which realize the limited difference functions. We show advantages of such elements consisting in encoding of variables by the photocurrent levels, that allows easily providing optical inputs (by photo-detectors (PD)) and optical outputs (by LED). The conception of construction of R MCL D consists in the use of a current mirrors realized on 1.5μm technology CMOS transistors. Presence of 55÷65 transistors, 1 PD and 1 LED makes the offered circuits quite compact and allows their integration in 1D and 2D arrays. In the presentation we consider the capabilities of the offered circuits, show the simulation results and possible prospects of application of the circuits in particular for time-pulse coding for multivalued, continuous, neuro-fuzzy and matrix logics. The simulation results of NOT, MIN, MAX, equivalence (EQ) and other functions, that implemented R MCL D, showed that the level of logical variables can change from 1 μA to 10 μA for low-power consumption variants. The base cell of the R MCL D have low power consumption

The paper considers results of design and modeling of continuously logical analog-to-digital converters (ADC) based on current mirrors for image processor and multichannel optical sensor systems with parallel inputs-outputs. For such multichannel serial-parallel analog-to-digital converters (SP ADC) it is needed base photoelectron cells, which are considered in paper. Its have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the continuously logical ADC of photocurrents and its base digit cells (ABC) and its simulations. We consider CL ADC for Gray and binary codes. Each channel of the structure consists of several base digit cells (ABC) on 20-30 CMOS FETs and one photodiode. The supply voltage of the ABC is 1-3.3V, the range of an input photocurrent is 0.1 – 10μA, the transformation time is 30ns at 5-8 bit binary or Gray codes, power consumption is about 1mW. One channel of ADC with iteration is based on one ABC-3(G) and SHD, and it has only 40 CMOS transistors. The general power consumption of the ADC, in this case, is only 50-100μW, if the maximum input current is 1μA. The CL ADC opens new prospects for realization of linear and matrix image processor and photo-electronic structures with picture operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers, and so forth.

We consider equivalency models, including matrix-matrix and matrix-tensor and with the dual adaptive-weighted correlation, multi-port neural-net auto-associative and hetero-associative memory (MP NN AAM and HAP), which are equivalency paradigm and the theoretical basis of our work. We make a brief overview of the possible implementations of the MP NN AAM and of their architectures proposed and investigated earlier by us. The main base unit of such architectures is a matrix-matrix or matrix-tensor equivalentor. We show that the MP NN AAM based on the equivalency paradigm and optoelectronic architectures with space-time integration and parallel-serial 2D images processing have advantages such as increased memory capacity (more than ten times of the number of neurons!), high performance in different modes (10 10 – 10 12 connections per second!) And the ability to process, store and associatively recognize highly correlated images. Next, we show that with minor modifications, such MP NN AAM can be successfully used for highperformance parallel clustering processing of images. We show simulation results of using these modifications for clustering and learning models and algorithms for cluster analysis of specific images and divide them into categories of the array. Show example of a cluster division of 32 images (40x32 pixels) letters and graphics for 12 clusters with simultaneous formation of the output-weighted space allocated images for each cluster. We discuss algorithms for learning and self-learning in such structures and their comparative evaluations based on Mathcad simulations are made. It is shown that, unlike the traditional Kohonen self-organizing maps, time of learning in the proposed structures of multi-port neuronet classifier/clusterizer (MP NN C) on the basis of equivalency paradigm, due to their multi-port, decreases by orders and can be, in some cases, just a few epochs. Estimates show that in the test clustering of 32 1280- element images into 12 groups, the formation of neural connections of the matrix with dimension of 128x120 elements occurs to tens of iterative steps (some epochs), and for a set of learning patterns consisting of 32 such images, and at time of processing of 1-10 microseconds, the total learning time does not exceed a few milliseconds. We offer criteria for the quality evaluation of patterns clustering with such MP NN AAM.

The paper considers results of design and simulation of analogue-digital converters (ADC) based on current mirrors for the multi-sensor systems with parallel inputs-outputs. Such ADCs are named us as multichannel serial-parallel analog-to-digital converters based on current mirrors (M SP ADC CM). Compared with usual converters, for example reading, a bit-by-bit equilibration, and so forth, the proposed converters have a number of advantages: high speed and reliability, simplicity, small power consumption, the big degree of integration in linear and matrix structures. We discuss aspects of the design of M SP ADC CM in Gray and binary codes. It is offered, investigated and simulated the 6, 8 and more digit M SP ADC CM in Gray code and binary codes. Each channel of the overall structure consists of several base digit cells (ABC), with options for low power consumption with only one such ABC and analog memory (less than 20 CMOS transistors). Base digit cells (АВС) of such M SP ADC CM, series-pipelined in structures, consist of 20-30 CMOS transistors, one photodiode, have low (1-3.3) V supply voltage, work in current modes with the maximum values of currents (10-40) μA. Therefore such new principles of realization of high-speed low-digital M SP ADC CM have allowing, as shown by simulation experiments, to reach time of transformation less than 20-30ns at 5-8 bits of binary code and Gray code and the power consumption 1-5mW. The quantity of easily cascadable АВС depends on multi-bit ADC, and makes n, and provides quantity of quantization levels equal N=2 n . Such simple structure of M SP ADC CM with low power consumption ≤3÷5mWand supply voltage (3-7)V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40 MHz, and can be increased up to 10 times) and accuracy (Δ quantization =156,25nA for I max =10μA ) characteristics are show. The range of optical signals, taking into account sensitivity of modern photo-detectors, can be 20-200 μW. Each channel of ADC, to reach the general power 50-100 μ W for low power consumption, can consist of only one such ABC and analog memory. To implement such serial ADC no more than 40 CMOS transistors are needed. The M SP ADC CM opens new prospects for realization linear and matrix (with picture operands) micro photo-electronic structures which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers, and so forth.