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In this paper, in-situ heat cooling with temperature monitoring is reported to solve thermal issues in electric vehicle (EV) batteries. The device consists of a thick graphene cooler on top of the substrate and a platinum-based resistive temperature sensor with an embedded heater above the graphene. The graphene layer is synthesized by using chemical vapor deposition directly on the Ni layer above the Si substrate. The proposed thick graphene heat cooler does not use transfer technology, which involves many process steps and does not provide a high yield. This method also reduces the mechanical damage of the graphene and uses only one photomask. Using this structure, temperature detection and cooling are conducted simultaneously using one device. The temperature coefficient of resistance (TCR) of a 1×1mm(2) temperature sensor on 1-im-thick graphene is 1.573×103 ppm/°C. The heat source cools down 7.3°C from 54.4°C to 47.1°C.

In this paper, a copper foil -thick grapheme (thin graphite sheet)-copper foil structure is reported to achieve mechanically strong and high thermal conductive layer suitable for heat spreading components. Since graphene provides much higher thermal conductivity than copper, thick graphene embedded copper layer can achieve higher effective thermal conductivity which is proportional to graphene/copper thickness ratio. Since copper is nonreactive with carbon material which is graphene, chromium is used as adhesion layer to achieve copper- thick graphene-copper bonding for graphene embedded copper layer. Both sides of thick graphene were coated with chromium as an adhesion layer followed by copper by sputtering. The copper foil was bonded to sputtered copper layer on thick graphene. Angstrom`s method was used to measure the thermal conductivity of fabricated copper- thick graphene-copper structure. The thermal conductivity of the copper- thick graphene -copper structures is measured as 686W/m·K which is 1.6 times higher than thermal conductivity of pure copper.

A linearized 2.3GHz CMOS power amplifier with AM-AM and AM-PM distortion correction is presented. The varactors are used at the driver amplifier load to correct the phase distortion and gate bias control of the PA to compensate the amplitude distortion. The proposed CMOS PA has been implemented in 0.13µm CMOS technology. The measured results show that P1dB is increased 1.6dB and PAE is improved from 5.5% to 9% at the condition of -28dB EVM, respectively.

This paper presents the performance characteristics of an air-suspended high-Q MEM inductor that is characterized based on an open-short deembedding scheme and used for accurate and reliable evaluation of the parasitic effects experienced from feed lines as well as contact pads. The validity and effectiveness of the de-embedding method are proven with a fixed-length MEM transmission line along with various feed-line topologies. The measured inductances of the 20-μm elevated transmission line provide consistent data, as compared to the simpler open de-embedding method. For more realistic and complicated MEM inductors with 1.5 and 2.5 turns, the characterized inductance values agree very well with the calculated data, based on the Greenhouse algorithm. The measured and calculated inductances are within the 5% range. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 43: 355–358, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20468

This paper presents the fabrication and electrical characteristics of the Integrated Field Emission Microsource (IFEMS) with multiple gates. The molybdenum field emission tip was made by filling cusp-like mold formed when a conformal film was deposited on the hole-trench. Each field emitter has a 1.8 μm-diameter extraction gate and a 1.4 μm-diameter focusing gate. To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP(Ethylene-Diamine Pyrocatechol) solution successively. The emission characteristics were measured and the influence of the focusing gate has been analyzed.

A very highly sensitive resist is difficult to simulate its resist profile because of its extreme difference of development rate which can be determined from absorbed energy when electron beam is exposed. We developed resist profile simulator named ELIS (Electron-beam LIthography Simulator) that can predict the development profile of a very highly sensitive resist: Hybrid scattering model, Gaussian beam convolution and its superposition were used for Monte Carlo simulation and the ray tracing model for resist development.

A 2×2 MIMO(multi-input multi-output) for m-WiMAX (IEEE 802.16e) / WLAN (IEEE 802.11n), multi-mode / wideband transceiver system was developed. To design the transceiver system, the RF architecture was redesigned for the overall system, and a MIMO antenna, quad-band switchable front-end module (FEM), and reconfigurable RFIC were developed. Using embedded PCB technology, the transceiver system was integrated. The system is multi-mode / multi-band based on a RF chain and MIMO type using a tunable single RFIC and multiple FEM. In this paper, a developed chip set was examined. Then, a multi-mode / multi-band RF transceiver system was developed and tested using a 2.3 GHz air signal.

This paper presents a method for improvements of radio frequency (RF) microelectromechanical systems (MEMS) switch which was previously reported at MEMS 2008 [1] and introduces a single-pole twelve-throw (SP12T) switch based on improved switch. The proposed switch was driven by a double stop (DS) comb drive, with a lateral resistive contact. Additionally, the proposed switch was designed to be bidirectionally actuated. A forward actuation connects between signal lines and contact part, and the output becomes on-state. A reverse actuation connects between ground lines and contact part, and the output becomes off-state. This can make ground lines have same bias, and improve the RF characteristics. The 2-stage cascade type SP12T switch was developed based on an arrangement of the proposed RF MEMS switches.

This paper presents the RF characteristics of the RF MEMS switch as the silicon substrate resistivity. The larger the resistivity of silicon substrate is, the larger the insertion loss of the RF MEMS switch is. When the RF MEMS switch is fabricated with the single crystalline silicon, the RF characteristics are changed by resistivity of silicon. It is necessary to study the change of RF characteristics as the substrate resistivity. The RF characteristics were simulated with different resistivity of silicon substrate. The RF MEMS switches were fabricated on each substrate with different resistivity. The RF MEMS switch was fabricated with the resistivity of 10 ohm-cm, the insertion loss of that is about 0.2 dB at 6 GHz. And the RF MEMS switch was fabricated with the resistivity of 500 Ohm-cm, the insertion loss of that is about 0.6 dB at 6 GHz.

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V/sub D/=2 V is 446 mS/mm for the 0.1 /spl mu/m n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 /spl mu/m to 0.1 /spl mu/m and good subthreshold characteristics are achieved for 0.1 /spl mu/m channel device.

In a deep submicron p-channel metal oxide field effect transistor (PMOSFET), the importance of the p+ poly-Si gate with less boron penetration and higher conductivity increases. With As implantation prior to B+ implantation, the conductivity of the p+ poly-Si gate was improved and the boron penetration was suppressed. These phenomena can be attributed to the enhancement of the grain growth in the As-preamorphized film and the retarded boron diffusion during annealing. DC conductivity of the film preamorphized by As+ ions at 180 keV and 4×1014 cm-2 was about 36% higher than that of the B implanted film without As preimplantation, in spite of the carrier compensation effect. Cross-sectional transmission electron microscopy (XTEM) micrographs show the bilayer with an upper layer of larger grain size ( ∼0.22 µm) and a lower layer of smaller grain size ( ∼0.03 µm) in the preamorphized and annealed film.

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si consumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the consumed Si source during Ti silicidation. This method was applied to the actual fabrication of the PMOSFET (p-channel metal oxide semiconductor field effect transistor) through the SES (selectively etched Si) technology.