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This article introduces a novel FIR filter using a Radix-2r multiplier combined with 4:2 and 3:2 compressors for denoising Electrooculography (EOG) signals. This approach replaces traditional ripple-carry adders with compressors to add the partial products generated by the Radix-2r multiplier, resulting in reduced delay and energy consumption. The FIR filter is implemented in gate-level Verilog HDL, verified using ModelSim and Altera DSP Builder, and synthesized with the Cadence RTL compiler. Compared to conventional designs, the proposed filter achieves a 71.48% reduction in area, 73.28% reduction in power, 51.84% reduction in delay, 86.22% reduction in the area-delay product (ADP), and 92.38% reduction in energy-per-operation (EPS), significantly outperforming the SOPOT filter. [ABSTRACT FROM AUTHOR]

An approximate carry select adder (CSLA) with reverse carry propagation (RCSLA) is showed in this work. This RCSLA was designed with reverse carry propagate full adder (RCPFA). In RCPFA structure, the carry signal propagates in the reverse direction that is from MSB part to LSB part, then the carry input has greater importance compared to the output carry. Three types of implementations were designed in RCPFA based on the design parameters. This method was applied to RCA & CSLA to design other types of approximate adders. These designs and simulations were done in CADENCE Software tool with 45 nm COMS technology. The design parameters of the three CSLA implementations with RCPFA are compared with the existing CSLA adders. [ABSTRACT FROM AUTHOR]

This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication ((x even ± x odd ) ∗ 0. 7 0 7 1 0 6) is implemented with R a d i x − 2 r multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A R a d i x − 2 r multiplier with 4:2 compressor technique is used to improve energy and delay. Compared to the previous architectures, the proposed architecture gives reduction in area, power, and delay. The proposed Haar wavelet architecture is implemented in gate-level Verilog HDL and synthesized with UMC 90-nm technology using Cadence RC compiler. When compared to the existing designs, the proposed architecture Haar DWT architecture synthesis results show reduction in latency of 32.32% and 31.46% of circuit area. [ABSTRACT FROM AUTHOR]

This paper presents a modified 2D Discrete Wavelet Transform (DWT) architecture with a proposed 16- bit Radix8 Booth multiplier. Existing architecture makes use of Canonic Sign Digit (CSD) representation and when replaced the CSD multiplier with the proposed 16-bit Radix8 Booth multiplier it achieves better performance with small area and low power. In proposed Radix-8 Booth multiplier, the necessary product terms are generated and the remaining terms are truncated. In this method, the n order bit required by the specific coefficient is obtained and the remaining n bits are truncated so that 2n bit output truncated to n bit. The modified 2D DWT architecture is proposed to enhance that it occupies less number of clock cycles, so that it improves in the speed of operation By comparing synthesis results for existing CSD multiplier and the proposed Radix-8 Booth multiplier achieves an improvement of nearly 29.02% Area Delay Product (ADP) and 26.13% Power Delay Product (PDP). [ABSTRACT FROM AUTHOR]