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In this paper, we propose a processing-in-memory of high bandwidth memory (PIM-HBM) scheme including system architecture and hardware structure. The proposed scheme embeds processing units into the logic layer of the HBM to expose an excess dynamic random-access memory (DRAM) bandwidth. With parallelized DRAM architecture and a high-speed through silicon via (TSV) structure, the proposed scheme successfully extends the DRAM bandwidth of PIM. Also, the total energy consumption is decreased by the reduced interconnection and capacitance-reduced channel structure. We designed the overall architecture and structure with physical feasibility for application to the current HBM. The logic layer and DRAM layers in the HBM are configured to embed the processing units and parallelize the DRAM channels. For high-speed data transfer with low interconnect energy, the TSV and silicon interposer channels are designed and analyzed in consideration of signal integrity (SI). Based on the physical design, we obtained the interconnect length in detail. The interconnect energy and delay of the silicon interposer and on-chip interconnect were modeled through a SPICE simulation. We analyzed the accurate effects of interconnect reduction caused by PIM. For overall system performance and efficiency analysis, a cycle-level architectural simulation was conducted. We successfully evaluated and analyzed the system performance for memory-intensive applications. As a result, the proposed PIM-HBM achieves 53% and 10.4% improvement on average in computing performance and energy efficiency compared to the conventional GPU-HBM.

In this article, we first measured through glass via (TGV) noise coupling and the effectiveness of shielding structures in a glass interposer. To analyze the noise coupling between signal TGVs, an open-ended structure is adopted. Glass interposer test vehicles were fabricated to verify the noise coupling between signal TGVs. With these test vehicles, noise transfer functions between signal TGVs were measured. Based on these measurement results and the equivalent circuit model, the noise coupling between signal TGVs was analyzed. To suppress this TGV noise coupling, shielding structures for the TGV noise coupling were proposed and verified. The proposed shielding structures include the variation of signal TGV pitches and the number of grounded shield TGVs, ground pads, and guard rings, respectively. The effectiveness of the proposed shielding structures was verified up to 20 GHz in frequency-domain measurements. Using the proposed shielding structures, the noise transfer function decreased by 9.4 dB at 5 GHz. Also, the effectiveness of the proposed guard ring structure was verified by a time-domain coupling noise simulation with clock signals at frequencies of 1 GHz. The proposed guard ring successfully suppressed the clock noise coupling between signal TGVs by 60.5% and 69.2% when a signal TGV pitchis 300 and 900 $\mu {\text{m}}$ , respectively.

In this article, we modeled, analyzed, and evaluated a large-scale memristor crossbar array in a neuromorphic system for a deep neural network (DNN) considering signal integrity (SI). Since hardware-based DNN using a memristor crossbar array operates in an analog way, it has serious reliability problems caused by interconnects, driver, and nonlinear memory cells. The interconnects including an on-chip signal and power/ground (P/G) mesh were modeled as circuit parameters from a full 3-D-electromagnetic (EM) simulation. The memristor was electrically modeled including its nonlinear characteristics. These models were configured into a $512 \times 512$ memristor crossbar array with drivers and peripheral circuits for the implementation of DNN. Then, we analyzed the component-level SI and nonlinearity for the interconnects and memristors, and the system level for the total array configuration. Finally, the regression of DNN in the memristor crossbar array was evaluated for verification of the analysis. All the analyzed SI and nonlinearity effects from the interconnects, memristor, and array configuration affected the regression. As the input voltage level decreased, the effect of the SI effect on accuracy became more dominant than that of the nonlinearity of the memristor effect. In terms of SI, it was verified that there is a tradeoff relationship between IR drop and crosstalk according to the interconnects’ size. Finally, the accuracy and power consumption were verified according to the array configuration in the system level as an important issue of the memristor crossbar array. Through the overall process, it was possible to analyze how the SI and nonlinearity effects affect the computational results in the neuromorphic system.

In this paper, we, for the first time, designed and analyzed differential high-speed serial links of the silicon interposer including differential through-silicon-via (TSV) channels for a high-bandwidth memory (HBM) graphic module. The meshed ground plane and various parameters were considered in designing the silicon interposer. In addition, superior designs were proposed to improve signal integrity (SI) for the differential channels in the redistribution layer, TSVs, and the meshed ground. SI of the silicon interposer was successfully analyzed, and the corresponding results were verified based on a full 3-D electromagnetic solver and circuit simulations. A number of RLGC parameters were extracted and calculated, then adopted to verify the simulation results. The simulation results for the differential characteristic impedance and insertion loss were compared with those of the equivalent circuit. A mixed-mode conversion matrix was utilized to analyze differential-mode transmission. Moreover, a model for differential TSV channels was proposed to precisely analyze the electrical characteristics. The eye-diagram simulation was conducted to evaluate SI of the proposed designs in terms of an eye-opening voltage and timing jitter. The eye-opening voltage of the proposed design was 0.594 V, which is 45.69% of a peak-to-peak voltage of the assumed peripheral component interconnect (PCI)-express 4.0 interfaces. It is expected that the analysis and design methodologies of differential high-speed serial links for a silicon interposer could be widely adopted in the semiconductor industry.

This paper, for the first time, proposes and verifies a new coaxial silicone rubber socket for high-bandwidth and high-density package test using a fabricated sample. In addition, this paper also characterizes and verifies the coaxial silicone rubber socket. Because of the proposed coaxial socket’s novel coaxial structure, the proposed socket successfully achieves the electrical performance improvement. For verification, we compare the proposed socket and the previous noncoaxial socket in time domain. The proposed socket has greater eye height and eye width in the measured eye diagram than those of the noncoaxial socket. Moreover, the slope in the eye diagram is also improved in the case of the proposed socket. Therefore, the measured eye diagram for the coaxial socket shows the improvement in electrical performances. This paper also characterizes the equivalent RLGC model for the coaxial silicone rubber socket. In order to verify the RLGC model, we compare the insertion losses and eye diagrams from measurement, 3-D electromagnetic simulation, and the proposed RLGC model, respectively. Their insertion losses are comparable up to 20 GHz. Furthermore, the obtained eye diagrams are almost identical at the data rate of 9.6 Gb/s. In conclusion, this paper successfully proposes, verifies, and characterizes a new coaxial silicone rubber socket for the first time.

Usually, modeling takes a long time because it depends on the engineer's experience and is done through repetitive tuning. In this paper, we propose a deep neural network (DNN)-based lumped circuit modeling method using an impedance curve. The proposed method provides a fast and accurate electrical circuit model of inductance (L), capacitance (C), and conductance (G) using a DNN. Since the LCG parameters are predicted by the impedance curve, it is flexible for various applications. For accurately predicting lumped circuit parameters, the DNN model is designed and trained through various case studies. As a result, the proposed method predicts 100% accuracy in inductance and conductance, and 92% accuracy in capacitance. In other words, the proposed method successfully models the electrical characteristics of various applications.

In this paper, we propose the through silicon via (TSV) array design optimization method using deep reinforcement learning (DRL) framework. The agent trained through the proposed method can provide an optimal TSV array that minimizes far-end crosstalk (FEXT) in one single step. We define the state, action, and reward that are elements of the Markov Decision Process (MDP) for optimizing the TSV array considering FEXT and train a deep q network (DQN) agent. For verification, we applied the proposed method to a 3 by 3 through silicon via array at stacked DRAM of High Bandwidth Memory (HBM). The network converged well, and as the result, the proposed method provided the optimal design that satisfies the target FEXT in which 3 dB lower than the initial design.

In this paper, we, for the first time, proposed the Reinforcement Learning (RL) based interconnection design for 3D X-Point array structure considering crosstalk and IR drop. We applied the Markov Decision Process (MDP) to correspond to finding the optimal interconnection design problem to RL problem. We defined interconnection state to the vector, design to the action and the number of bits, crosstalk and IR drop are considered as the reward. The Proximal Policy Optimization (PPO) and Long Short-Term Memory (LSTM) are used to RL algorithms. The proposed interconnection design model is well trained and shows convergence of reward score in 16×16, 32×32 and 64×64 cases. We verified that the trained model finds out optimal interconnection design considering both memory size and signal integrity issues.

In this paper, we first propose a policy gradient reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for 2.5-D/3-D integrated circuits (ICs) using a transformer network. The proposed method can provide an optimal decap design that meets target impedance. Unlike previous value-based RL methods with simple value approximators such as multi-layer perceptron (MLP) and convolutional neural network (CNN), the proposed method directly parameterizes policy using an attention-based transformer network model. The model is trained through the policy gradient algorithm so that it can achieve larger action space, i.e. search space. For verification, we applied the proposed method to a test hierarchical power distribution network (PDN). We compared convergence results depending on the action space with the previous value-based RL method. As a result, it is validated that the proposed method can cover ×4 times larger action space than that of the previous work.

In this paper, we propose the design of a HDMI 2.1 connector for 8K TV considering signal integrity (SI). Also, we firstly measure the proposed HDMI 2.1 connector. To achieve the high data rate, connector should be designed by considering not only mechanical characteristics but also electrical characteristics. We design the HDMI 2.1 connector considering SI including characteristic impedance, differential insertion loss and attenuation to crosstalk ratio (ACR). We revise the structure of metal pins and dielectric materials for improving the SI performances. Proposed HDMI 2.1 connector was verified by time-domain and frequency domain simulation using the 3D electromagnetic (EM) simulator. Proposed HDMI 2.1 connector showed improve SI performance than previous connector. Also, proposed connector was verified through measurement. With the proposed HDMI design, it shows better SI characteristics at the 24 Gbps which is expected to next generation HDMI connector’s data rate.

In this paper, we firstly proposed a thermal transmission line (TTL) based embedded cooling structure for advanced thermal management of a next-generation high bandwidth memory (HBM) module. Thermal issues are critical to the development of HBM and 2.5D/3D ICs. The proposed TTL based embedded cooling structures can be one of the promising thermal management solutions for the 2.5D/3D ICs. The previous embedded cooling structures have thermal management limitations of the difficulties of cooling the internal heat of the 2.5D/3D ICs each layer. The proposed TTL transfers internal heat to the coolant to lowering junction temperature. Moreover, we checked the fabrication feasibility of the TTL with through silicon vias (TSVs). By using 3D electromagnetic (EM) and 3D fluent simulations, we analyzed the proposed TTL considering signal integrity (SI) and thermal integrity (TI). SI analysis showed the TTL does not contribute critical SI issues for HBM on-chip TSV channels. TI analysis provided the thermal management superiority of the TTL. As a result, it showed the improvement of TI of HBM module decreased HBM junction temperature by 4.789°C compared to the previous embedded cooling structure.

A hardware-based artificial intelligence (AI) operation using memristor crossbar array is a promising AI computing architecture due to its energy-efficiency. It mimics the computational form of matrix-vector multiplication, which is the main AI operation and is implemented in an analog way. However, the reliability problem is serious because of the hardware-based operation. In this paper, we propose a hybrid circuit model of a hardware-based deep neural network (DNN) for a large-scale memristor crossbar array in terms of signal integrity (SI) problems. After DNN classification training for the optimized weight matrix in memristors, we demonstrated and analyzed the effect of SI on DNN accuracy using the proposed model. It is possible to analyze the effect of the SI problems due to interconnection at the crossbar on the reliability of computational accuracy through this hybrid circuit model. Simulated accuracy of DNN inference is degraded up to 36.4% in the worst case due to IR drop and ringing depending on the physical dimension of array interconnection and operating frequency in a memristor crossbar array.

In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

In this paper, we first propose a fast and accurate deep neural network (DNN) model extension method for signal integrity (SI) applications. Reusing pre-trained weights of DNN model, the model can be extended when new training data are given. Instead of updating whole weights of DNN in traditional machine learning (ML) approaches, fine-tuning of a part of weights can accelerate training. For verification, we applied the proposed method to regression model of peak time domain reflectometry (TDR) impedance of through hole via (THV) and classification model of through silicon via (TSV) void defects. Training time of the proposed method were 0.3 s and 2.3 s respectively, which are 99 % and 82.3 % reduction compared to the traditional approach. Moreover, test accuracy of the proposed method achieved 99.2 % and 100 %, respectively.

In this paper, we, for the first time, propose the modeling and verification of 3-dimensional storage class memory (SCM) using new memory with high speed circuits for core operation. For the memory analysis with the simulation, the RC model of interconnections and core operation circuit models are combined in the same simulation environment. Therefore, we modeled the memory elements using passive resistances and voltage controlled switches in circuit simulation system for compatibility. To verify the proposed model, we compared the characteristics of the memory cell with the behavior model which verified to the experimental data. The overall characteristics of memory cell model are similar with the conventional behavior model. In addition, we simulated the core operation of 3-dimensional resistive SCM with the proposed models and verify the applicability in time-domain.

As technology advanced, the demand for data bandwidth has been increasing. To meet this demand, the data rate of the channel has been increased, which causes a lot of signal integrity problems. Optimization of the channel is important to solve these problems. Channels are usually optimized with the empirical knowledge of signal integrity designers. However, it is not accurate and requires numerous iterations. On the other hand, a Bayesian optimization method can quickly find optimized parameter values without relying on empirical knowledge. Therefore, this paper proposes a method for optimizing high-speed channel using Bayesian optimization. The proposed method optimizes the frequency response result such as insertion loss, and find the optimal physical dimension parameters. Finally, the optimized results of the proposed method were verified by comparing all the simulation results in the range of the channel.

In this paper, for the first time, we propose a processing-in-memory in high bandwidth memory (PIM-HBM) architecture for high bandwidth systems with low dynamic random-access memory (DRAM) access costs. The main concept of the proposed PIM-HBM architecture is to embed processing units into a logic base of high bandwidth memory (HBM) to decrease the energy consumption and latency of interconnections as the physical length between core and DRAM decreases. To verify the proposed PIM-HBM architecture, we designed on-chip and on-interposer I/O channels using a CMOS 0.18 µm process. We extracted channel parasitic using an electromagnetic (EM) solver and performed a SPICE simulation to compare the system performance of the proposed architecture with the conventional HBM. As a result, the performance of the proposed PIM-HBM architecture is successfully verified by reducing energy consumption and latency of interconnections by 77 % and 79 % compared to the conventional HBM system.

Recently, various high-speed connectors are used for the data transmission. With the high data rate, it is important to design the high-speed connectors considering not only mechanical but also electrical characteristics. In this paper, we propose a 10 Gbps USB 3.2 Gen 2 Type-C connector for TV set-top box. For the high-speed data transmission, the signal integrity (SI) including characteristic impedance, insertion loss and return loss should be considered. We verified the improved SI performance of proposed connector based on time-domain and frequency domain simulation using 3-D electromagnetic (EM) solver. Furthermore, with the proposed connector design, it shows superior SI characteristics at 20 Gbps which is expected to next generation connector’s data rate.

In this paper, we, for the first time, modeled and analyzed through-silicon vias (TSVs) in the multi-conductor transmission. TSV is one of the essential technology for 2.5-D/3-D ICs, Definitely, a significant number of TSV must be integrated for the direct vertical interconnections. In this point of view, it is important to propose the accurate modeling and analysis for the multiple coupled-TSVs. Firstly, we utilized the loop inductance matrix to model the self- and mutual-inductance respectively. With the assumption of the quasi-TEM propagation, the capacitance and conductance matrix were subsequently calculated to model the self- and mutual- components. The proposed multiconductor TSVs model was compared with an electromagnetic (EM) solver. The analysis of TSVs was performed based on the insertion loss at frequencies ranging from 0.01 GHz to 20 GHz. From the proposed modeling methodology, the evaluation of an electrical performance for the multiple numbers of TSVs becomes possible. In addition, signal coupling paths were discussed based on the proposed equivalent circuit model and it was observed that the equivalent conductance path is dominant in the signal couplings.

In this paper, we, for the first time, modeled and analyzed through-silicon via (TSV) with an embedded high-density metal-insulator-metal (MIM) capacitor. For 2.5-D/3-D ICs, this technology could be a potential solution to improve electrical performance. We conduct the modeling and the proposed model were compared with an electromagnetic (EM) solver, to evaluate signal and power integrity (SI/PI). The analysis was performed based on the insertion loss and impedance in the frequency range from 0.01 GHz to 20 GHz. The dominant factors to determine the electrical characteristic were analyzed depending on the frequency range. In order to model the TSVs, the concept of loop inductance was applied. Then, the capacitance and conductance between the TSVs were calculated respectively including the MIM capacitance. From the results of modeling and EM simulations, it is predicted that the TSVs are beneficial to improve SI not PI. Because the equivalent capacitance is decreased in the low frequency range under 200 MHz and the equivalent conductance is increased in the high frequency range above 200 MHz

In this paper, we design and analyze receiver channels of a glass interposer for a 5G small cell front end module (FEM). In RF systems, a 50 ohm impedance matching is important for RF channels to guarantee the target RF sensitivity of the RF system. Receiver channels of glass interposers for the 5G small cell FEM are designed, analyzed and characterized up to 40 GHz considering the impedance matching. Using the designed receiver channels, the glass interposer based the 5G small cell FEM is designed and analyzed up to 40 GHz.

Recently, semiconductor devices are becoming more diverse and scaled down for various applications such as electronic devices, communication systems and automotive components. Such applications can utilize sputtered shielding structures to solve electromagnetic interference (EMI) issues. To reduce the EMI issues, copper and nickel are commonly used as sputtered shielding materials. To analyze the shielding effectiveness, we applied the Schelkunoff's theory. For the verification of the Schelkunoff's theory, we simulated and measured the shielding effectiveness of copper and nickel at the frequency range between 100 kHz and 10 MHz using two identical coils.

3D XPoint memory is one of the new memory using phase change memory (PCM) and ovonic threshold switch (OTS) with 20 nm 3-dimensional cross array structure. This memory is non-volatile and has better performance in terms of memory process speed than NAND flash memory and memory density than DRAM. The space between interconnections are close so, the voltage coupling affects to the adjacent interconnections during read operation. In this paper, we analyzed the 3D XPoint memory with memory size variation during read operation considering signal integrity (SI). For the analysis, we assumed the overall structure of the 3D XPoint memory and modeled the memory cell that consist of PCM and OTS as behavior model and the interconnections as RC model with 3D electromagnetic (EM) simulator. We fully simulated the 3D XPoint memory including memory behavior model, RC model of interconnections and peripheral circuits such as the addressor and current sense amplifier. With variation of the memory size during read operation, there are SI issues such as voltage coupling and drop trends through the interconnections.

Silicon interposer with high bandwidth memory (HBM) has been developed to achieve a terabyte/s bandwidth graphic card module. However, silicon interposer still has critical drawbacks regarding the complexity of fabrication and manufacturing cost. Especially, expensive through-silicon-via (TSV) process has become a serious problem for cost reduction. An innovative package substrate called embedded multi-die interconnect bridge (EMIB) becomes alternative solution for memory industries to reduce manufacturing cost and complexity of fabrication process of silicon interposer. Consequently, signal and power integrity (SI/PI) design and analysis of silicon based EMIB package substrate becomes essential, because it will be dominantly affected to HBM interface. In this paper, superior SI designs of EMIB is proposed and analyzed considering manufacturing cost. In addition, the impact on hierarchical PDN impedance due to EMIB is discussed and we proposed further direction for PI improvement. Proposed designs and analysis of EMIB package substrate are expected to be widely adopted in memory industries for next generation HBM interface.