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Article number 9400400 A fully differential Miller op-amp with a composite input stage using resistive local common-mode feedback and regulated cascode transistors is presented here. High gain pseudo-differential auxiliary amplifiers are used to implement the regulated cascode transistors in order to boost the output impedance of the composite input stage and the open-loop gain of the op-amp. Both input and output stages operate in class AB mode. The proposed op-amp has been simulated in a 130nm commercial CMOS process technology. It operates from a 1.2V supply and has a close to rail-to-rail differential output swing. It has 156dB DC open-loop gain and 63MHz gain-bandwidth product with a 30pF capacitive load. The op-amp has a DC open-loop gain figure of merit FOMAOLDC of 174 (MV/V) MHz pF/µW and large-signal figure of merit FOMLS of 3(V/µs) pF/µW. Consejería de Economía y Conocimiento of Junta de Andalucía P18-FR-4317 Consejo Nacional de Ciencia y Tecnología (España) A1-S-43214 Agencia Estatal de Investigación TEC2016-80396-C2

A family of capacitively coupled alternating current (AC) amplifiers featuring ultra-low (below 1 Hz) corner frequency is presented. This is achieved by using high-gain devices which actively boost feedback resistance and thus reduce corner frequency. This procedure is often termed, though with a different purpose, as 'bootstrapping'. The proposed architectures are very general and admit several possible practical implementations. To demonstrate their usefulness, the circuits are implemented with two operational amplifiers (OA), but other active devices such as operational transconductance amplifiers (OTAs) can be alternatively used. All circuits have been theoretically analyzed, extensively simulated and measured, exhibiting high-pass cutoff frequencies as low as 30 mHz. This work was supported by AEI/FEDER (Grant PID2019‐107258RB‐C32), Ministry of Universities (grant BES‐2017‐080418), and Public University of Navarra.

The knowledge of wireless signal distribution within an urban scenario can provide useful information to users as well as to enhance connectivity and device operation or to perform municipal logistics based on crowd density and user mobility patterns. In this work, a distributed wireless mapping system, based on a combination of opportunistic nodes such as smartphones which map geolocated WiFi access point connection and received power levels, and a cloud-based information gathering architecture is described. The proposed system has been tested in the framework of the Smart City platform of the city of Pamplona, providing signal distribution heat maps, which can be used for multiple municipal services. The authors want to thank the European Commission for its financial support through the Holistic and Integrated Urban Model for Smart Cities - STARDUST project (H2020-SCC-2017 Grant agreement ID: 774094), and specifically the local partners involved such as the Pamplona City Council, Mancomunidad de la Comarca de Pamplona (MCP) and National Renewable Energy Centre of Spain (CENER-CIEMAT).

An efficient class-AB OTA with enhanced output current, slew rate, open loop gain, and gain bandwidth is presented. The circuit is based on a class-AB input stage with adaptive biasing, and an output stage with dynamically biased cascode transistors. It can deliver output currents 100 times larger than the bias current with a total quiescent power dissipation of 72 µW. Measurement results of a 180 nm CMOS test chip prototype show slew rate, gain bandwidth, and open loop gain enhancement.

En este trabajo podemos ver la vida del maestro de educación física en un colegio rural, dónde se enseña, pero no sólo contenidos académicos, sino que se lleva a cabo algo más, podríamos llamarla, una educación individualizada; dónde las características del entorno son la clave de que esta sea así. Podemos ver como es la vida del maestro a la hora de hacer frente a problemas como el hecho de no tener instalaciones, de tener un número ínfimo de alumno, dar clases de una hora y media… incluso de tener aulas multinivel. Eso sí, se podrá apreciar como la docencia aquí hace que el trabajo sea placentero, donde se conocen todos los alumnos entre sí, la relación con padres y vecinos del pueblo es más cercana, lo que hace que el desempeño de su educación sea algo más fácil. En general, apreciaremos como algo que parece inhóspito en una primera instancia, donde nada más llegar vemos que posee pocos recursos materiales, pocas instalaciones…se convierte en un lugar que nos despierta nuestra imaginación y creatividad aprendiendo a trabajar con pocos recursos y aprovechar el medio que nos rodea., Universidad de Granada. Facultad de Ciencias de la Educación. Grado en Educación Primaria

En la presente contribución se discute la necesidad de analizar el problema de la escasa presencia de la mujer en los estudios de ingeniería de telecomunicación. Se describe una encuesta en curso para indagar los factores de la segregación de género en esta carrera. Asimismo, se propone trasladar al aula medidas que capten una mayor presencia femenina.

Tesis Univ. Granada. Departamento de Didáctica y Organización Escolar. Leída el 3 de febrero de 2006

La labor del experto de la educación especial pasa por dinamizar los procesos educativos dentro del centro escolar. Se ha de facilitar la inclusión del alumnado de necesidades específicas de apoyo educativo e involucrar al conjunto de la comunidad educativa en el proceso de cambio, en la toma de decisiones y el trabajo compartido con este alumnado. Se pretende profundizar en el conocimiento de la educación especial y la legislación. Se divide en cinco bloques: aspectos introductorios y teóricos; aspectos organizativos de la Educación Especial; aspectos didácticos de la Educación Especial; programas y recursos para la atención a la diversidad; y asesoramiento y orientación a la comunidad educativa. Madrid Biblioteca de Educación del Ministerio de Educación, Cultura y Deporte; Calle San Agustín 5 -3 Planta; 28014 Madrid; Tel. +34917748000; biblioteca@mecd.es ESP

A new high performance second-generation CMOS current conveyor architecture is presented. It is built using a differential flipped voltage follower as its input buffer stage and a cascode current mirror as output stage. It is characterized by very low output impedance. It provides gain independent high bandwidth when used to implement a programmable gain voltage amplifier. Simulation and experimental results in AMI 0.5µm CMOS technology are provided to validate the characteristics of the design.

In this paper a novel transconductor based on floating gate techniques that performs current multiplication for tuning is presented. The multiplication is achieved using transistors operating in weak and moderate inversion together with floating voltage sources implemented conveniently by floating capacitors. Besides, a tuning scheme is proposed to set the transconductance parameter accurately. The resulting circuit features compactness, low voltage operation, and rail-to-rail input range. Measurement and simulation results using a 0.5um CMOS technology are presented to confirm all the circuits and strategies proposed.

A novel CMOS tunable transconductor is presented. The circuit operates in classAB hence featuring power efficiency. The internal feedback employed and the use of a linearized triode transistor for voltage-to-current conversion allows achieving high linearity. Rail-to-rail input range is obtained by using floatinggate transistors. Measurement results for a test chip prototype in a 0.5µm standard CMOS process show an IM3 of -52.13dB at 1MHz for a 2Vpp input and a power consumption of 2.2mW.

This paper presents the implementation of a crossquad circuit suitable for low-voltage operation. The proposed cell exploits a dynamic positive feedback gm boosting technique to achieve linear voltage-to-current conversion, while it manages to work with low-voltage with no extra bias current and minimal additional hardware. Results for a 0.5 m CMOS implementation supplied at 3 V show a 0.972 % voltage-tocurrent accuracy, improving the 0.867 % accuracy of a previously reported cross-quad topology also suitable for lowvoltage operation which is based on folded transistors. Ministerio de Ciencia e Innovación (PET2007-00336, PET2008-0021) Agencia Española de Cooperación Internacional para el desarrollo - Programa de Cooperación Interuniversitaria e Investigación Científica (AECI-PCI) (A/018704/08) Universidad de Zaragoza (UZ2008-TEC-08)

Comunicación presentada al First Internacional Workshop on Marine technology. Villanova i La Geltrú (Barcelona), 2005. The goal of this project is to design a low-cost smart accelerometer, making use of a piezoelectric element as basic sensing material, and adding a mixed-mode conditioning circuit.

Trabajo presentado al XV Simposium Nacional de la Unión Científica de Radio (URSI '00), Zaragoza, 2000 A novel phase-locked loop scheme is proposed in this paper, whose main distinguishing features are infinite hold-in range, pull-out range fractionally constant and also a ripple fractionally constant. To this end, it incorporates a variable gain amplifer and a frequency tunable loop filter. The driving application is the on-chip automatic tuning of slave filters, although the PLL architecture can be employed in many other applications. This work has been suported by the CICYT under grant TIC 97-418-C02-01.