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A frequency downscaling technique for enhancing the accuracy of analog lock-in amplifier (LIA) architectures in giant magneto-impedance (GMI) sensor applications is presented in this paper. As a proof of concept, the proposed method is applied to two different LIA topologies using, respectively, analog and switching-based multiplication for phase-sensitive detection. Specifically, the operation frequency of both the input and the reference signals of the phase-sensitive detector (PSD) block of the LIA is reduced through a subsampling process using sample-and-hold (SH) circuits. A frequency downscaling from 200 kHz, which is the optimal operating frequency of the employed GMI sensor, to 1 kHz has been performed. In this way, the proposed technique exploits the inherent advantages of analog signal multiplication at low frequencies, while the principle of operation of the PSD remains unaltered. The circuits were assembled using discrete components, and the frequency downscaling proposal was experimentally validated by comparing the measurement accuracy with the equivalent conventional circuits. The experimental results revealed that the error in the signal magnitude measurements was reduced by a factor of 8 in the case of the analog multipliers and by a factor of 21 when a PSD based on switched multipliers was used. The error in-phase detection using a two-phase LIA was also reduced by more than 25%. [ABSTRACT FROM AUTHOR]

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 μm CMOS technology that validates the proposed scheme are presented. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-μm CMOS process. Experimental results show a greatly improved slew rate by factors 30–60 and gain-bandwidth product by factors 11.5–17 when compared to a classical Class-A OTA. The circuits are operated at ±1-V supply voltage with only 10 μA of bias current. [ABSTRACT FROM AUTHOR]

A continuous-time implementation of a voltage-mode analog rank order filter is presented. The proposed circuit features high speed, high precision, and simple circuit implementation. The overall architecture exhibits linear increase of complexity with the number of inputs (0(n)), at the rate of seven transistors per input1 Rank is easily programmable with the tail current for all rank order values from the Max to the Mm case, and the programmed function is accurate for a wide range of tail currents. More Over, unlike previously reported rank order structures the precision of the proposed circuit does not rely on perfect matching of all input transistors. Simulations as well as experimental results are presented that verify the functionality and performance of the proposed circuit. [ABSTRACT FROM AUTHOR]

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-μm implementation achieves a SFDR of 68 dB and a THD of -66.5 dB using a dual supply of ±1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion. [ABSTRACT FROM AUTHOR]

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-μm CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-μA quiescent currents and ±1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal. [ABSTRACT FROM AUTHOR]

High-speed analog rank-order filters (ROFs) can find application in real-time image and speech processing, data compression, communications, neural and fuzzy networks. In this paper, a more compact CMOS implementation of a continuous-time analog ROF is presented. In this implementation described in Section II, hardware complexity grows also linearly with the number of inputs, but at the rate of only two transistors per input. It is based on a multiple input differential structure and requires, in its basic form, only two transistors per input.

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very Iow-voltage applications. [ABSTRACT FROM AUTHOR]

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-µm CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-µA peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm² of silicon area and features 0.96 mW of static power consumption. [ABSTRACT FROM AUTHOR]