Search

A novel characterization technique for DRAM test cell arrays is presented. The new method permits the extraction of subthreshold IV-characteristics of the cell transistor and its threshold voltage with no DC contacts to the source. The DRAM cell is viewed as an equivalent circuit of resistors and capacitors, whose values can be determined by sweeping the frequency of the AC-impedance bridge. Using this technique, it is possible to characterize the cell transistor in its natural habitat without resorting to special test structures.

Measurements on n-type indium antimonide down to 0.3K are described of the resistivity in a magnetic field (0-40 kG) both parallel and perpendicular to the current, and of the Hall effect. Increases of resistivity by a factor of 1010 are observed before the resistivity becomes too high to measure provided special care is taken over the preparation of the surface of the specimen. A saturation of resistivity with increase of magnetic field is sometimes observed and this is attributed to the effect of a conducting surface layer. The resistivity approximates to the form rho -1= rho 01-1 exp(-E1/kT)+ rho 03-1 exp(-E3/kT). The E1 region is identified with magnetic freeze-out and the E3 region with electrons hopping between donor centres. Good agreement is obtained between theory and experiment for the magnetic field dependence of rho 03.

One of the primary factors controlling 16M DRAM cell concept choice is that of sufficiently small leakage. Trench cell leakage to the substrate, to the adjacent trench and to neighboring transistor and bitline contact have been determined here for reduced geometry Trench Cells using a manufacturable 4M process. It is shown that the ``Super Shrink Trench Cell'' is a viable 16M DRAM candidate insofar as leakage limitations are concerned.