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This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si x )Ge1- x O y , which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced ${D}_{{\text {IT}}}$ , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum ${V}_{{\text {OV}}}$ of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm- ${L}_{g}$ n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.

integration requires development of low thermal budget process modules. High-quality SiO 2 interfacial layer (IL), obtained up to now only by high-temperature (≥850°C) oxidation or exposure, is crucial for pMOS NBTI reliability. In unannealed IL’s grown at reduced temperatures, we show that unrelaxed interface strain induces high defect densities, with physics-based NBTI modeling suggesting excessive hydroxyl-E’ defect formation due to Si-O bond stretch. Based on ab-initio theoretical insights, we demonstrate an atomic hydrogen treatment to passivate SiO 2 defects at low temperatures (100-300°C), which is shown to be vastly more effective than high pressure molecular hydrogen exposure, and to yield an SiO 2 quality and reliability surpassing a 900°C oxide.

We demonstrate multiple ways to reduce the D IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D IT reduction, while nitridation of the HfO 2 dramatically reduces D IT by negating an ALD TiN-induced D IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si 0 7 Ge 0 3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $\text{D}_{\text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $\text{Gm}_{\text{SAT}}/\text{SS}_{\text{SAT}}$ of 5.4 at 73 nm Lg.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

Al diffusion into gate stack leads to EOT reduction.Process reduces the EOT at low temperature (400?C) and is suitable for replacement gate processes.Extensive interface studies support the electrical measurements.Reactions are in agreement with thermodynamical considerations. The continued device scaling demands the reduction of the equivalent oxide thickness (EOT) below 1nm. For HfO2-based gate stacks, the interfacial SiO2 limits the EOT scaling. A low EOT can only be achieved if the interfacial layer (IL) is reduced to its physical limit of ~4i?. Such thin EOT are achievable if redox reactions within the gate stack are employed in order to reduce SiO2. This study reports on the use of an Al layer in combination with a TiN metal electrode to reduce the IL and achieve lowest EOT values. The lowest EOT achieved was 4.6i?. However, the scavenging process was found to strongly depend on the thermal budget after Al deposition. The presented process adapts a standard metal-inserted poly-Si flow (MIPS) prior to Al deposition, but may also be an option to control IL regrowth.

We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options are optimized to demonstrate ring-oscillator functionality for fin width down to ∼4nm.

Ultrathin EOT-values are achieved by using optimized processing conditions and interface layer scavenging in metal-gated (TiN and TaN) HfO"2 based planar and bulk-FinFET devices. EOT values down to 4.5A(T"i"n"v~8.5A) in the planar devices and T"i"n"v

A sub 1-nm equivalent oxide thickness (EOT) gate stack with conduction band edge effective work function is demonstrated with an ALD deposited HfO2/SrTiO3 based composite material. An EOT reduction of 0.2 nm as compared to the HfO2 reference is obtained after applying a high thermal budget in a gate first transistor flow. A comparison with ALD HfO2/La2O3 and HfO2/MgO composite stacks is made. Results suggest that the EOT reduction and threshold voltage shift (Vt) are determined by the Sr, La or Mg diffusion inside the dielectric stack and into the interface oxide after a thermal treatment. The onset of this diffusion is temperature dependent and differs from stack to stack.

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al2O3 layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiOpropcapped with 9 Aring of thin Al2O3obtains a low long-channel Vt of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm2 /V ldr s at 0.8 MV/cm (92% of universal value), a negligible equivalent- oxide-thickness (EOT) increase of 0.1 Aring (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of -0.7 V. This indicates that thin Al2O3obtains caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al2O3-capped HfSiOprop is not favorable because it increases the Vt by 50-140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5-0.8 Aring and the Vt instability by 5-13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, high-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO2 interface.

To increase CMOS device performance, new materials are introduced in the gate stack (high-k dielectrics, metal gates) and the transistor channel (Ge, III-V). In this work, we study the Atomic Layer Deposition (ALD) of hafnium based gate dielectric oxides. Depositing by means of surface controlled reactions implies that the chemical sites at the surface can determine the growth behavior. First, the starting surface effect is analyzed for HfO 2 ALD on Ge and GaAs substrates. Either substrate inhibition or enhancement occurs, both associated with an initial regime of island growth The presence of oxygen enhances the GPC in the first reaction cycle. Second, the steady ALD of ternary oxides (hafnium silicate, aluminate, zirconate) is discussed HfCl4 (and ZrCl4) chemisorption are much less affected by the composition of ternary oxides than by the starting surface. On the other hand, the SiCl4 chemisorption rate is significantly affected by the Hf-content of hafnium silicates. © The Electrochemical Society.

The continuous need for enhanced performance of the integrated circuits demands for the development of new device structures other than the conventional planar MOSFET. Multi-gate transistors – such as the FinFET – are considered to overcome the technological challenges as they can be scaled down to very short gate lengths. Furthermore, scaling of the device dimensions requires the introduction of gate dielectrics with a permittivity κ, higher than that of SiO2. As the FinFET consists of a vertical silicon fin, the high-κ dielectric has to be deposited on silicon with both a (100) and (110) crystal orientation. Moreover, this substrate topology requires the use of a deposition technique that offers excellent conformality and step coverage of the as-grown material. These characteristics are ensured by using Atomic Layer Deposition (ALD) to grow the gate dielectric.

Atomic Vapor Deposition (AVD®) and MOCVD of TaCN-based films are studied for high work function needed for PMOS Gate-first designs. Work functions as high as 4.85eV and 4.92eV are achieved on HfSiON and HfSiO high k dielectrics, respectively. The film composition was varied from pure Ta2N to TaC films which improve the work function as well as thermal stability. The high work function was different depending on whether different underlying high k dielectrics and N compositions were used. The approaches for obtaining high work function and the impact of underlying high k films are discussed. After detailing the physical and chemical characteristics of MOCVD and AVD® TaCN films, this paper correlates the deposition technologies to the high work function values obtained by extraction from flatband voltage / equivalent oxide thickness (EOT) measurements.

Downscaling of CMOS gate stacks requires introduction of ultra-thin high-k dielectrics such as HfO2. Atomic Layer Deposition has excellent characteristics for depositing such films. We have compared HfCl4/H2O and TEMAH/O3 ALD between 245ºC and 370ºC. Growth behavior and electrical performance are discussed as function of process parameters. Precursor choice has a clear impact on HfO2 deposition process and device performance. Both precursors demonstrate good growth nucleation on -OH rich starting surfaces. TEMAH shows better nucleation on low -OH density surfaces, suggesting a potential advantage for interface optimization towards low EOT. However, with HfCl4 lowest leakage currents were obtained as well as excellent interface scaling results by using well chosen interface layers. The leakage current of TEMAH/O3 layers strongly depends on the ALD process temperature and oxidizer dose, suggesting the impact of C impurities on the dielectric properties. Overall the HfCl4 approach seems to be the most promising solution.

Accurate thickness and composition control for ultra-thin films is demonstrated for the atomic layer deposition (ALD) of La2O 3 and HfLaO. Growth studies indicate a linear growth without substrate inhibition for La2O3 and HfLaO ALD on HfSiO and hydroxylated SiO2, respectively. Layer closure studies on HfSiO show a fast La2O3 layer closure. Vt-tuning in a high thermal budget NMOS transistor flow is established (i) by inserting sub-nm La2O3 capping layers between the HfSiON gate oxide and the TaCx metal electrode and (ii) by replacing the HfSiON gate oxide film by HfLaO. Changing the La2O3 capping layer thickness from 0 till 1 nm, results in tunable Vtshifts up to ∼ 600mV while retaining low equivalent oxide thickness (EOT), high mobility, and low gate leakage current. Hf-rich HfLaO gate dielectric layers resulted in a V t-shift of ∼ 250 mV and EOT values down to 1.1 nm. © The Electrochemical Society.

Atomic layer deposition (ALD) with HfCl4 as a precursor is widely used for HfO2 fabrication. Due to the nature of the precursor under study, i.e., HfCl4 and H2O, the presence of chlorine residues in the film due to insufficient hydrolysis is eminent. Obviously, the chlorine residue in the HfO2 film is suspected to affect the quality of the HfO2 film. In this paper, The authors reduced the concentration of chlorine residues by increasing the H2O oxidant pulse time in between the deposition cycles from 0.3 to 10 and 90 s. Time-of-flight secondary ion mass spectrometry analysis shows that this decreases the chlorine concentration in the HfO2 film by more than one order of magnitude. However, time-dependent dielectric breakdown analysis shows that the lifetime remains quasi unaffected (within identical error bars) for the different injection cycles. Charge pumping analysis was done by varying both pulse frequency and amplitude to investigate the creation of defects, but negligible differences were observed. Therefore, the presence of chlorine residues has no significant impact on the trap generation and reliability of ALD HfO2 layers, and this result corresponded with the mobility result. The experimental picture is confirmed with first-principle calculations that show that the presence of chlorine residues does not induce defect levels in the bandgap of HfO2

The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO2/HfO2/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-kappa bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 degC spike for t=1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 degC for t=60 s). For 1000 degC spike-annealed films, where the highest SiO2/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO2 and the IL which increases for high-temperature processing

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (L G ) around 22 nm, an improvement which is predicted by modeling to extend down to L G T ) values in bulk FinFET devices with L G down to 22 nm. Furthermore, selective removal of the nWFM is confirmed physically down to L G ∼16 nm providing further evidence that the process is scalable towards N7 dimensions.

In this paper the effects from the high-k dielectric thickness and the metal gate deposition technique on the mobility of n-channel MOS transistors are investigated. The results reveal mobility degradation due to an increase of charge density in the dielectric and / or at the material interfaces, not efficiently compensated by the screening effect from the gate. We correlate this mobility degradation to the reduction observed in a comparison between metal and poly-Si gated MOSFETs. It is shown that the mobility can be improved by using different metals deposition technique, which indicates that the mobility reduction is related to the deposition technique.

We present what to our best knowledge is the first forward operating silicon light-emitting diode (LED) in fin-FET technology. The results show near-infrared (NIR) emission around 1100 nm caused by band-to-band light emission in the silicon which is uniformly distributed across the lowly doped active light-emitting area. We also propose further improvements to exploit the full potential of this structure.

A scalable multi-V T enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-V T is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack T inv , J G , D IT and reliability as well as the device performance are shown to be unaffected by the multi V T process.

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET INV -normalized G M,SAT,INT of 6.7 nm.mS/μm, the Si 0.3 Ge 0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

In this letter, we report that by using a thin dysprosium oxide (Dy2O3)cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (Vt) of poly-Si/TaN gated n-FETs can be modulated to match that of the reference poly-Si/SiON devices, with a significantly scaled equivalent oxide thickness, a much reduced gate leakage, improved time-zero-break-down characteristics, and a minor degradation of the long channel devices mobility. These effects are attributed to the formation of a DySiON layer formation after full device fabrication due to the intermixing between the Dy2O3 cap and the SiON layer, as evidenced by a cross-sectional transmission-electron-microscopy measurement.

Introduction: Series resistance (R series ) is a crucial factor for technology optimization and benchmarking [1–3]. R series is typically extracted in the bias conditions where R series dominates, i.e., linear regime and high Vgs by comparing multiple gate lengths. However this simple extraction is very challenging for sub22nm CMOS devices as changing a device length / width may change mobility or R series . For instance, this is the case for SiGe where the built-in stress effect [5,6] increases the channel mobility thus making the standard extraction difficult. The case is even more compelling for the bulk finfet case where the length width and height may not be known with the necessary precision and the gate stack itself may introduce (un)wanted stress components. As any R series extraction do rely critically on assumptions, in this paper we will first test the applicability and limits of several R series extraction techniques [1–3] and then use the best of both to gain new insights on the finfet and SiGe technology.

In this work, we report high performance Si .45 Ge .55 Implant Free Quantum Well (IFQW) pFET with high drive current of 1.28mA/um at Ioff=160nA/um at channel length/width of 30nm/0.16um (Vdd=−1V). This is enabled by 1) low temperature process which maintains the integrity of the high mobility of Si .45 Ge .55 channel, 2) embedded SiGe (eSiGe) stressor which is fully compatible with SiGe channel and 3) relaxation of unwanted transversal stress at narrow width channel which results in a significant mobility boost (1.9x mobility improvement from active width of 10um to 0.1um).

This work demonstrates the successful integration of 0.85nm-EOT Si 0.45 Ge 0.55 -pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si 0.55 Ge 0.45 -pFETs, an I ON of 630µA/µm at L G_POLY = 35nm with I OFF = 100nA/µm and V DD = −1V has been achieved without any epi-S/D boosters. Significant improvements at lower V DD have also been confirmed through complex circuit simulations and validated by experimental results.

We report low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3A reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12A, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

This paper overviews integration challenges of low-V T gate-first CMOS featuring one metal gate electrode and one host dielectric with Al 2 O 3 and La 2 O 3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V T enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.

We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-VT nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaVT relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar VT tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

Recently, thin rare-earth oxide dielectric capping layers between the high-k and metal gate have been used to modulate the threshold voltage (Vt) of MOSFETs [Kirsch et al., 2006]. In Dy2O3-capped high-k based devices, we observe an anomalous PBTI behavior where the Vt decreases during stress. Results suggest that there are two competing mechanisms - diffusion of preexisting positively-charged species and electron trapping. The charged species is likely located in the mixed high-k dielectric and associated with the interaction between the host dielectric, cap, and metal gate.

A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low VT values of plusmn 0.25 V and unstrained IDSAT of 1035/500 muA/mum for nMOS/pMOS at IOFF=100nA/mum and |VDD|=1.1 V are demonstrated on a single wafer. This was achieved using Hf-based high-k dielectrics with La (nMOS) and Al (pMOS) doping, in combination with a laser-only activation anneal to maintain band-edge EWF and minimal EOT re-growth. The laser-only anneal further results in improved LG scaling of 15 nm and a 2 Aring TINV reduction over the spike reference.

We show for the first time that conduction and valence band-edge effective work functions (WF) are achieved simultaneously by one single Dy2O3 capping layer on HfO2 for both nMOS and pMOS with TaCx-based metals. Low Vt's (0.23 and -0.36 V) are obtained without degrading the EOT-JG scalability and hole mobility. A model based on competing intermixes of cap/host dielectric and cap/metal is proposed to explain the positive WF shift with TaCxNy and the negative shift with TaCx as compared to the uncapped HfO2 reference. Finally, by developing a novel nitridation process to modify TaCx into TaCxNy, this work shows that single-metal-single-dielectric gate stacks are feasible, allowing cost-effective low-Vt CMOS integration.

A technique has been developed to fabricate transistors using a continuously scaled 0-2.5 nm SiO2 interface layer between a silicon substrate and high-κ dielectric on a single wafer. Transistor results are promising with good mobility values and drive current. The slant etching process has no detrimental effect on the electrical characteristics of the Si/SiO2 interface. This technique provides a powerful tool to examine the effect of process variations on device performance. It has been used to demonstrate that reducing source/drain anneal temperature, from 1000degC to 700degC, results in a significant mobility degradation, for SiO2 interlayer thickness less than 1.0 nm. Above this thickness, the mobility and DIT are relatively independent of anneal temperature