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The aphid Chaetosiphon fragaefolii Cockerell, 1901 is an agricultural pest and known vector of strawberry viruses. To better understand its biology and systematics, we performed a genomic analysis on C. fragaefolii collected from Quinalt strawberry plants from Pacific Grove, Monterey county, California, USA using Oxford Nanopore and Illumina sequencing. The resulting data were used to assemble the aphids complete mitogenome. The mitogenome of C. fragaefolii is 16,108 bp in length and contains 2 rRNA, 13 protein-coding, and 22 tRNA genes (GenBank accession number LC590896). The mitogenome is similar in content and organization to other Aphididae. Phylogenetic analysis of the C. fragaefolii mitogenome resolved it in a fully supported clade in the tribe Macrosiphini. Analysis of the cox1 barcode sequence of C. fragaefolii from California found exact and nearly identical sequences to C. fragaefolii and Chaetosiphon thomasi Hille Ris Lambers, 1953, suggesting the two species are conspecific.

A VLSI implementable, massively parallel, digital, stochastic neural network architecture with on-chip learning is described which can be used to address video/image compression applications. Color information in images is usually encoded as a means to reduce the data needed to transmit high resolution video images over a lower bandwidth communication system. A neural net approach can be used for such a compression scheme since it can be trained to map a set of patterns from a k-dimensional space to a 1D space very easily. The training algorithm is implemented as a cross correlation between previously calculated weights and global errors. These simple calculations are performed by each processing unit with information available in their local memories, thus, no transfer of information between neurons is necessary. This feature allows for the synchronous updating of all the weights, which optimizes the inherent parallel nature of the neural network architecture, making the design an excellent candidate for VLSI implementation as an SIMD architecture. By incorporating the learning portion on-chip, an appreciable reduction in computing time is possible. The stochastic nature of the learning algorithm, and a simulated 'annealing' process, allows it to convergence to a global minimum. The architecture is synthesized from an HDL description using powerful design and analysis tools which allow for many performance trade- offs and fault coverage to be done by the compiler before the final design is sent for fabrication.© (1995) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.