Search

The manipulation of fast domain wall motion in magnetic nanostructures could form the basis of novel magnetic memory and logic devices. However, current approaches for reading and writing domain walls require external magnetic fields, or are based on conventional magnetic tunnel junctions (MTJs) that are not compatible with high-speed domain wall motion. Here we report domain wall devices based on perpendicular MTJs that offer electrical read and write, and fast domain wall motion via spin-orbit torque. The devices have a hybrid free layer design that consists of platinum/cobalt (Pt/Co) or a synthetic antiferromagnet (Pt/Co/Ru/Co) into the free layer of conventional MTJs. We show that our devices can achieve good tunnelling magnetoresistance readout and efficient spin-transfer torque writing that is comparable to current magnetic random-access memory technology, as well as domain wall depinning efficiency that is similar to stand-alone materials. We also show that a domain wall conduit based on a synthetic antiferromagnet offers the potential for reliable domain wall motion and faster write speed compared with a device based on Pt/Co. Domain wall devices based on perpendicular magnetic tunnel junctions with a hybrid free layer design can offer electrical read and write, and fast domain wall motion driven via spin-orbit torque.

Building quantum computers requires not only a large number of qubits with high fidelity and low variability, but also a large amount of analog and digital components to drive the qubits. Larger arrays of solid-state qubits with high fidelity and low variability require improvements in fabrication processes and array layout design co-optimized with the underlying hardware technology. Here we outline progress on 300mm fabrication of qubit devices and on classical CMOS components to enable the quantum system. We describe work on superconducting qubits and spin qubits in Si, both types of devices fabricated on 300mm experimental platforms and discuss challenges related to variability. Massive electrical characterization is key over wide temperature range is key to enabling system upscaling for QC.

Novel mask absorber designs are catching the attention of the EUVL community due to their ability to mitigate mask 3D effects. Material selection is part of such an optimization. We propose several candidates as novel EUV lithography mask absorbers, namely TaTeN, Ru–Ta, and Pt–Mo alloys. The choice of these materials is based on their theoretical performance evaluated by EUV imaging simulation based on their complex refractive index N ( λ ) = n ( λ ) + ik ( λ ) , where the optical constants n and k relate to the phase velocity and the absorption of electromagnetic radiation with a wavelength λ, respectively. The materials are deposited as thin films on Si substrate with an additional Ru layer to mimic the cap of the multilayer mirror on the real mask. The experimental n and k values are determined by analyzing EUV reflectivity data obtained using a 13.5-nm synchrotron EUV radiation. The imaging simulation presented consists of calculating several imaging metrics including non-telecentricity, normalized image log-slope, and threshold-to-size for specific use cases using the novel absorber. It also compares the proposed materials with the reference TaBN absorber. TaTeN shows higher absorption than TaBN and refraction closer to 1, which improves phase matching for a high k absorber. The refractive index of Ru–Ta and Pt–Mo alloys exhibits a large difference from that of air and provides the required phase shift of attenuated phase shift masks. The characterizations of these materials target the requirements of an EUVL mask: durability for mask cleaning, mask lifetime, and etchability for mask patterning. The stability is first tested against several standard mask cleaning solutions by a beaker test for up to 24 h. The samples are also exposed to hydrogen plasma to imitate the working environment in an EUV scanner. Concerning material patterning, chemical reactive ion etch is applied for preliminary tests. A proper etch recipe is found for TaTeN with a good etch rate (about 60 nm / min) and good selectivity to the Ru underlayer (Ru etch is negligible).

We present a detailed study of the impact of damage minimizing patterning schemes on the electrical performance of perpendicular STT-MRAM devices at array level, compatible with 22 nm CMOS technology node. By employing a novel patterning scheme involving physical ion beam etch (IBE), etchback and oxidation steps, we show reduction in switching voltage (32%), switching energy (20%) and an improvement in the reliability window (20%), as compared to the conventional physical etch. These improvements are reported in conjunction with 10-year data retention ( $\Delta$ ), WER ∼ 1 ppm and 108 cycling on 1 kbit cells. We attribute these improvements to a significant reduction in free layer (FL) damage. Morphological studies highlighting the minimization of oxygen penetration and the subsequent bird's beak formation around the FL strongly support our understanding. These results highlight a possible tuning knob in the IBE process to improve the device performance significantly and may help to improve the tail bits.

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

The coherence of state-of-the-art superconducting qubit devices is predominantly limited by two-level-system defects, found primarily at amorphous interface layers. Reducing microwave loss from these interfaces by proper surface treatments is key to push the device performance forward. Here, we study niobium resonators after removing the native oxides with a hydrofluoric acid etch. We investigate the reappearance of microwave losses introduced by surface oxides that grow after exposure to the ambient environment. We find that losses in quantum devices are reduced by an order of magnitude, with internal Q-factors reaching up to 7 $\cdot$ 10$^6$ in the single photon regime, when devices are exposed to ambient conditions for 16 min. Furthermore, we observe that Nb2O5 is the only surface oxide that grows significantly within the first 200 hours, following the extended Cabrera-Mott growth model. In this time, microwave losses scale linearly with the Nb$_2$O$_5$ thickness, with an extracted loss tangent tan$\delta$ = 9.9 $\cdot$ 10$^{-3}$. Our findings are of particular interest for devices spanning from superconducting qubits, quantum-limited amplifiers, microwave kinetic inductance detectors to single photon detectors., Comment: 5+11 pages, 5+7 figures, 0+7 tables

We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300 mm CMOS fab on full wafers which clears the path for large scale integration. This proof-of-concept thus offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications.

Novel mask absorber designs are calling attention of the EUVL community due to their ability to mitigate mask 3D effects. Material selection is part of such optimization [1]. In this paper we propose several candidates as novel EUV lithography mask absorbers, namely TaTeN, Ru-Ta and Pt-Mo alloys. The choice of these materials is based on their theoretical performance evaluated by EUV imaging simulation based on their complex refractive index N(λ) = n(λ) +ik(λ), where the optical constants n and k relate to the phase velocity and to the absorption of an electromagnetic radiation with a wavelength λ, respectively. The materials are deposited as thin films on Si substrate with an additional Ru layer to mimic the cap of multilayer mirror (MLM) on the real mask. The experimental n and k values are determined by analyzing EUV reflectivity data obtained using a 13.5 nm synchrotron EUV radiation. The imaging simulation presented in this paper consists of calculation of several imaging metrics like non-telecentricity, normalized image log-slop (NILS), and threshold-to-size for specific use cases using the novel absorber. It also compares the proposed materials to the reference TaBN absorber. TaTeN shows higher absorption than TaBN and refraction closer to 1, which improves phase matching for a high k absorber. The refractive index of Ru-Ta and Pt-Mo alloys exhibits a large difference to that of air and provides the required phased shift of attenuated phase shift masks [2]. The characterizations of these materials target the requirements of an EUVL mask: durability for mask cleaning, mask lifetime and etchablity for mask patterning. The stability is first tested against several standard mask cleaning solutions by beaker test up to 24 hours with the film structure monitored by X-ray reflectivity analysis. The samples are also exposed to hydrogen plasma to imitate the working environment in a EUV scanner. Material integrity is checked with Rutherford backscattering spectroscopy before and after the exposure. Concerning material patterning, chemical reactive ion etch is applied for preliminary tests. A proper etch recipe is found for TaTeN with good etch rate (about 60 nm/min) and good selectivity to Ru underlayer (Ru etch is ignorable).

In next-generation EUV imaging for foundry N5 dimensions and beyond, inherent pitch- and orientation-dependent effects on wafer level will consume a significant part of the lithography budget using the current Ta-based mask. Mask absorber optimization can mitigate these so-called mask 3D effects [1-3]. Last year at the SPIE Photomask and EUVL conference [4,5], EUV mask absorber change is recognized by the community as key enabler of next-generation EUV lithography. Through rigorous lithographic simulations we have identified regions, based on the material optical properties and their gain in imaging performance compared to the reference Ta-based absorber [6]. In addition, we have established a mask absorber requirement test flow to validate the candidate material to the full mask supply chain. In this paper we discuss in more detail Te- and Ru- based alloys which cover these different improvement regions. Candidate materials are evaluated on film morphology, stability during combined hydrogen and EUV loading, and thermal and chemical durability. The EUV optical constants are measured by EUV reflectometry, and preliminary results of plasma etching are shown to enable patterning.

We propose a field-free switching SOT-MRAM concept that is integration friendly and allows for separate optimization of the field component and SOT/MTJ stack properties. We demonstrate it on a 300 mm wafer, using CMOS-compatible processes, and we show that device performances are similar to our standard SOT-MTJ cells: reliable sub-ns switching with low writing power across the 300mm wafer. Our concept/design opens a new area for MRAM (SOT, STT and VCMA) technology development., Presented at VLSI 2019 Circuit and Technology Symposium, JFS4p5

In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.

The read performance of a spin-transfer torque magnetic random-access memory device is based on the tunnel magnetoresistance of the magnetic tunnel junction cell, which is a function of the resistance values at low and high resistance states of the magnetic layers. To ensure a robust tunnel magnetoresistance value and high yield, magnetic tunnel junction pillar patterning process should have a good local critical dimension uniformity. In this paper, we screen several patterning techniques, such as dry development rinse material-based tone reversal besides the standard patterning, as well as different resists and underlayer materials to improve the local critical dimension uniformity at 50nm pitch extreme ultraviolet pillar printing. The results of the best litho process obtained show an improvement above 20% for the local critical dimension uniformity performance. The performance metrics such as the process windows analysis, pillar circularity and the critical dimension uniformity have also been checked for the promising litho process options. Moreover, the transfer of the post-litho improvements to the etch process have been checked and qualified after several layers of hardmask etch.

We present the development of Nb/Al–AlO x /Nb trilayer stacks and the implementation of a full 300 mm process flow for the fabrication of trilayer-based superconducting qubits. Room temperature electrical characterization of tens of thousands of Josephson junctions showed good agreement between blanket resistance-area (RA) product and RA product of processed wafers. Cross-bridge Kelvin resistor structures with dimensions ranging from 200 nm to 1.2 μm were tested and exhibited excellent yield and exceptionally low resistance variability down to

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400 °C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 A without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 A CoFeB polarizer from 125% to 145% for a similar RA product after a 300 °C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 A CoFeBTa reference layer spacer can even withstand annealing at 400 °C for 90 min and can retain a TMR value of 100% at RA 10 $\Omega \cdot \mu \text{m}^{2}$ , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL.

At breakdown conditions, large current flows in STT-MRAM devices. We experimentally show that this large current causes significant self-heating of 200-300°C, which impacts the reliability extrapolation to operating conditions. By measuring and analyzing breakdown at various temperatures and on different MgO thickness, we successfully incorporate self-heating into the breakdown model. We find that the 10 year lifetime is underestimated by a factor 103 at 63-percentile, to even 107 when applying percentile scaling to 1 ppm.

We present a scaled device based on magnetic domain wall (DW) transport for logic applications. The device consists of multiple magnetic tunnel junctions (MTJs) connected by the same magnetic free layer (FL). Magnetic domain walls are injected by spin-transfer torque (STT) at the input MTJs and are sensed by tunneling magnetoresistance (TMR) at the output MTJ after propagation through the FL. Logic functions can be built by merging several domain walls. By enabling real-time detection of long range DW transport, we demonstrate a spintronic component which can be used for either Boolean or non-Boolean logic.

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ., presented at VLSI2018 session C8-2

For the first time, we report on 400°C compatible top-pinned perpendicular magnetic tunnel junction (MTJ) stacks with dual MgO free layer for STT-MRAM applications. Using a texture-inducing parallel-coupling barrier layer (TICPB), we enforce the pinning layer and control diffusion, which enables BEOL compatibility while keeping TMR as high as 184%. In addition, we demonstrate that using such synthetic ferro-magnetic stack (SFM) design with TICPB layer allows a free layer off-set control and a switching current of 3.8 MA/cm2 in 25 nm e-CD devices.

Current EUV mask technology uses Ta-based metallic absorber layer, on top of a reflective multilayer mirror. Multiple studies have shown that the optical constants and the required 50-70nm thickness of Ta-based metallic absorber at EUV wavelength, do not offer an optimal wafer image, and, for example, produce images with pitch and illumination dependent best focus shifts for patterns at Foundry N5 dimensions. Alternative metal absorbers with higher absorptivity than Ta, such as Ni and Co have been proposed and, in simulation, show improved imaging at

The nanometer thin MgO barrier and the large write currents for STT-MRAM, result in an endurance bottle neck due to oxide breakdown. In this paper we present an in-depth analysis of the impact of processing on barrier breakdown, including etch techniques (ion beam etch and reactive ion etch), post etch treatments and variations of the spacer layers in the MRAM stack. We find that variability in breakdown characteristics can be significantly reduced using an optimized etch. Secondly we propose an oxygen scavenging model to explain the different reliability behavior for various stack configurations.

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall (DW) motion. In particular, it is a significant step toward the realization of a majority gate, even though further downscaling may be required. To our knowledge, this is the first fabrication of a cross-shaped free layer shared by several perpendicular MTJs. The fabrication process can be generalized to any geometry and any number of MTJs. Thus, this framework can be applied to other spin logic concepts based on magnetic interconnect. Moreover, it allows exploration of spin dynamics for logic applications, Comment: submitted to Japanese Journal of Applied Physics

In this work, we address the charge trapping properties of Ge dangling bond (DB) defects – GePb1 centers as typified by electron spin resonance spectroscopy (ESR) – found at the interfaces between condensation-grown Si1−xGex (0.28

In the quest for materials with a lower dielectric constant and/or a higher Young’s modulus, new results on advanced low-k films are reported. These films are fabricated using a sequence of three process steps: a PECVD co-deposition of matrix skeleton and porogen, a remote plasma to remove the porogen and a UV cure to strengthen the film. In this study, most emphasis was put on the optimization of the remote plasma and of the UV cure step. In this way it was possible to obtain a film with dielectric constant as low as 1.82 and another with a dielectric constant of 2.02 combined with a Young’s modulus higher than 5 GPa. Besides, this series of films showed also a very good resistance against 0.5% HF etching. FTIR analyses indicated that during this HF etching a C–F bond is formed. A model for the HF etching of this porous low-k material is proposed.

Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not outperform current state of the art uni-axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi-axially strained Ge grown on top of SiGe Strain Relaxed Buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the post-CMP and pre-epi cleans which are required to obtain contamination free SiGe surfaces to enable defect free strained Ge growth without reoccurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20 nm thick Ge epitaxially grown on top of SiGe Strain Relaxed Buffers with 85% Ge with a surface roughness as low as 1.6 Å (as measured on areas of 10×10 µm2).

In this work, digermane (Ge 2 H 6 ) is investigated as low temperature Ge precursor for Chemical Vapor Deposition. High quality Ge epitaxial growth on Si substrates is reported at temperatures as low as 275 °C and a specific Ge 2 H 6 surface reaction is proposed to explain the growth mechanism at those very low temperatures. In addition, we highlight that Ge 2 H 6 provides solutions, not covered by conventional GeH 4 , for various original Ge-based materials: direct deposition of amorphous Ge layers directly on dielectric or metallic surfaces, as well as the epitaxial growth of smooth, fully strained, monocrystalline GeSn layers on Ge substrates.

Further improving complementary metal oxide semiconductor (CMOS) performance beyond the 15 nm generation likely requires the use of high mobility materials like Ge for pMOS devices. However, Ge pMOS devices made in relaxed Ge do not out-perform current state-of-the-art uni-axially strained Si pMOS devices. This explains the current interest in compressively strained Ge like bi-axially strained Ge grown on top of SiGe strain relaxed buffers. From a device integration point of view, the surface smoothness of the strained Ge layer is an important parameter, which has so far not widely been reported in literature, in contrast to other parameters like the material quality (crystallinity) and the threading dislocation density. In this paper we report the capability of chemical mechanical polishing (CMP) to reduce the surface roughness of the SiGe strain relaxed buffers and the post-CMP and pre-epi cleans, which are required to obtain contamination free SiGe surfaces and to enable nearly defect free strained Ge growth without re-occurrence of the surface roughening. We will demonstrate the epitaxial growth of fully strained 20–40 nm-thick Ge epitaxially grown on top of SiGe strain relaxed buffers with 85% Ge with a surface roughness as low as 1.6 A (measured on areas of 10×10 μm 2 ).

© 2018 Author(s). Analogous device parameters in both the parallel (P) and anti-parallel (AP) states ensure a symmetric spin-transfer-torque magnetic random-access memory operation scheme. In this study, however, we observe an increasing asymmetry in the performance metrics with operating temperature of the bottom-pinned perpendicular magnetic tunnel junction (p-MTJ) devices. A temperature-dependent increase in the contribution of the stray field is observed in the tunneling magnetoresistance loop analysis. The switching current for P-to-AP decreases by 30% in the thermally activated switching regime by increasing the temperature from 300 K to 400 K, while it remains similar for AP-to-P. In addition, with the same temperature range, the thermal stability factor for the P state decreases 20% more than that for the AP state. We attribute those observations to the increase in the overcompensation of the stray field from the synthetic anti-ferromagnet structure. Saturation magnetization (M S ) of the [Co/Pt] x -based multilayers is much less affected by temperature [M S (400 K)/M S (300 K) = 97%] compared to that of the CoFeB-based multilayers (88%). Such an impact can be more severe during the electrical switching process due to the Joule heating effect. These results suggest that, to understand and to evaluate the performance in a wide range of temperatures, it is crucial to consider the contribution of the entire magnetic components in the p-MTJ stack. ispartof: APPLIED PHYSICS LETTERS vol:113 issue:14 status: published

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wall-based logic technology.

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 107 cm− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

We report on the fabrication and characterization of thin SiGe on insulator (SGOI) with high Ge content by the condensation technique. While one of the objectives of this report is to describe the process and give a complete characterization of the obtained substrates, the main intention is to focus on the fundamental understanding of key phenomena involved in the Ge condensation method. In particular, we will describe the oxidation kinetic using the conventional Deal and Grove model and show that for such process, since the thickness of oxide grown is large and since the oxide formed is pure SiO2, the oxidation kinetic can be modeled with the same parameters as those used for pure Si. Next, we will discuss the relaxation of the formed SGOI layer using linear elastic theory framework and evidence that even though the condensation method makes use of long high temperature treatments, the obtained layer are not in their equilibrium state and their relaxation is frustrated. However, we will show that it is still possible to predict their relaxation rate and that it is observed to increase with increasing Ge content. This poses some limitations in terms of defectivity of such substrates as they are inevitably partially relaxed. Expanding the analysis of relaxation and defect nucleation, we will finally discuss an approach to decrease the defect density and consider its drawbacks.

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials. Complementary integration of different materials on Si can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates on standard Si STI wafers. This reduces the fabrication cost of these virtual substrates as it omits the complicated isolation scheme in blanket Ge. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are compatible with uni-axial stress techniques. Both modules include an anneal at 850 {degree sign}C to reduce the threading dislocation density down to 4x108 cm-2 and 1x107 cm-2, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

The electrical impact of threading dislocations in strained-germanium (s-Ge) grown on a strain-relaxed Si0.2Ge0.8 buffer is investigated by means of the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of p+n and n+p junctions fabricated in these layers. For comparison, reference devices with a two to three orders of magnitude lower threading dislocation density (TDD) have also been studied. While the leakage current of the s-Ge diodes is about two decades higher, indicating an overall correlation with TDD, the impact of a post-growth anneal cannot be explained by a removal of TDs. Instead, it is believed that the heat-treatment-induced improvement of the reverse current is associated with the removal of point defect clusters from the SiGe buffer layers. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

An overview is given of the defect aspects with respect to Ge-on-Si materials and devices, with emphasis on the impact of post-growth thermal budget on the structural and electrical epi-layer characteristics. The observations on annealed thick and thin epitaxial layers on Si can be explained based on a thermodynamic model for the minimum density of threading dislocations (TDs). It is also demonstrated that for the present processing conditions, the leakage current of Ge CMOS compatible p+n junctions becomes independent of the TD density at about 10E7/cm2.

In the first part of this work we studied the effect of annealing time and temperature on the degree of threading dislocations density (TDD) reduction in epitaxial Ge films grown by CVD on Si. We show, that one-step controlled nitrogen annealing at temperatures above 800 °C can decrease TDD of thick (1.6 µm) Ge layers with 1 order of magnitude from 1E+ 08/cm 2 down to 1E+ 07/cm 2 . Our results indicate that when temperature is high enough (> 800 °C) time does not play a role anymore. Thus for a temperature of 850 °C the same degree of TDD reduction can be achieved for 3 as well for 30 min. In the second part of the work we demonstrate that the combination of cycled epi growth and high temperature annealing although beneficial for TDD reduction deteriorates the crystalline quality of the layers due to significant Si out-diffusion and SiGe formation. Ge on Si substrates with lower defect densities have been further characterized by leakage current measurements on diode structures. Our results indicate that the reduction of drain to bulk leakage is insignificant and does not correspond to 1 order of magnitude reduction in TDD. We therefore conclude that threading dislocations are not the dominant factor for reduced device performance.

In the first part of this work, the fabrication of silicon germanium-on-insulator substrates (SGOI) by the Ge condensation technique was studied. Ge atomic fractions as high as 93% have been obtained while maintaining nice structural properties of the films. We show that these layers exhibit a large compressive strain and that the strain can be lowered by introducing some annealing steps in argon ambient during the condensation. SGOI substrates with a Ge atomic fraction of 75% were subsequently used as template for the growth of strained epitaxial Ge layers. Because of the important strain in the SGOI, the temperature for the in-situ bake prior to the growth has to be carefully selected in order to avoid relaxation. Ge layers with compressive strain up to −1% and thicknesses up to 40 nm have been obtained. The crystal quality, roughness and thermal stability of the strained Ge layers were finally evaluated.

The purpose of this paper is to evaluate the impact of the laser anneal on the thermal stress induced defect creation in Si1-xGex S/D junctions. It is shown that several factors play a key role in the motion of the glide dislocations during the laser anneal process, when huge thermal stress gradients are present in both lateral and vertical directions: firstly, the stress levels prior to a post-epi implantation; secondly, the ion implantation conditions and finally, the laser energy beam conditions. Nomarski inspections of preferentially etched Si1-xGex/Si hetero-epitaxial junctions have been performed in order to analyze the laser-induced morphology changes. Additionally, I-V measurements were employed to further investigate the leakage current enhancement due to the thermal stress induced defect creation in the embedded Si1-xGex S/D junctions. Both analysis methods resulted in fully consistent results, revealing an increase in motion of dislocations and dislocation density only for the splits that already showed some relaxation induced-extended defects before the laser annealing process. Moreover, the only conditions where the extended defects prior to the laser anneal were observed were when a post-epi ion implantation was processed in the epilayers with 25%Ge (the highest Ge content studied).

Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.

It is shown that the high density of threading dislocations (TDs) and, more specifically, the high density of point defects associated with it and present in our strained Ge epitaxial layers on a Si 0.2 Ge 0.8 relaxed buffer layer degrades the mobility and the leakage current of pMOSFETs and p + n junctions fabricated therein. Annealing in the range 550–650 °C prior to gate stack deposition improves the device performance, although there is no marked change in the TD density. From this, it is concluded that the annealing may reduce the density of point defects grown in during the epitaxial deposition.