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PurposeThe purpose of this research was to develop a new process to bond silicon (Si) chips to low carbon steel substrates using pure tin (Sn) without any flux.Design/methodology/approachIron (Fe) substrates were first electroplated with a Sn layer, followed by a thin silver (Ag) layer that inhibits Sn oxidation thereafter. It is this Ag capping layer that makes the fluxless feature possible. Fluxless processes are more environmentally friendly and more likely to produce joints without voids. The Si chips were deposited with Cr/Au dual layer structure. The bonding process was performed at 240°C in vacuum. The Sn joint thickness was controlled by spacers during the bonding. Scanning electron microscopy images on cross sections exhibited quality joints without visible voids. Energy dispersive X-ray spectroscopy analysis was used to detect joint compositions.FindingsIt was revealed that the Sn layer was bonded to a Si chip at the Cr–Sn interface and to the Fe substrate by forming an FeSn2 intermetallic compound (IMC). The IMC is only 1.1 to 1.5 µm in thickness. Thin IMC is highly preferred because IMC deforms a little in accommodating the coefficient of thermal expansion (CTE) mismatch between Si and Fe. Shear test results showed that the fracture forces of the samples passed the military criteria by a wide margin.Originality/valueThis new fluxless bonding process on Fe should make Fe or low carbon steel a more likely choice of materials in optical modules and electronic packages.

Growth behavior of the intermetallic compound (IMC), FeSn2, was investigated in the liquid Sn/solid Fe reaction couple over the annealing temperatures from 250 °C to 400 °C. Low-carbon steel AISI 1018 was chosen to make Fe samples. The morphology and thickness of the IMC formed between Sn and Fe were examined using scanning electron microscopy (SEM). In addition, energy-dispersive X-ray spectroscopy (EDX) and X-ray diffraction (XRD) were used to confirm that the IMC is FeSn2. The growth kinetics of FeSn2 was modeled by parabolic law and empirical power law. Based on the models, the growth constants, the activation energy, and the time exponents were established at different annealing temperatures. It was found that the time exponent values obtained by fitting with empirical power law deviate from 0.5, meaning that volume (bulk) diffusion is not the only rate-controlling process in the liquid Sn/solid Fe reaction couple. Also, a variation in the time exponent values is indicative that the growth behavior is correlated with grain size growth and irregular grain morphology at different annealing stages. The results of this research show that AISI 1018 steel can readily react with Sn to form IMC on the interface. This is an essential requirement of soldering action using Sn-rich solders.

Silver solid solution phase with indium has been discovered to have great mechanical properties and anti-tarnishing property, as shown in the results of our previous study. It is important to know the stress vs. strain curve before adopting this material in industrial applications. The growth of the homogeneous silver solid solution phase with indium is first described. The X-ray diffraction (XRD) patterns and scanning electron microscope/energy dispersive X-ray spectroscopy (SEM/EDX) results are reported to verify the chemical composition of silver solid solution phase with indium samples. Based on the results, one could reversely determine the indium element composition in (Ag)-xxIn solid solution by examining the lattice constant value using XRD for unknown compositions. The preparation of ASTM tensile test samples and tensile test experimental setting are explained in details. The intrinsic mechanical material properties of silver solid solution phase with indium, i.e., characteristic stress vs. strain curves, are presented and analyzed, with pure silver stress vs. strain curve in comparison. According to the experimental results, silver solid solution phase with indium exhibits low yield strength, high ultimate tensile strength, and large elongation value before fracture, compared to pure silver. In addition, fractography of the fracture surface of the tested sample has been studied to confirm the superior ductility of silver solid solution phase with indium. These superior mechanical properties may bring silver solid solution phase with indium new applications in various industries such as electronics and brazing.

© 2015 Springer Science+Business Media New York Solid-state processes of bonding 1 mm copper (Cu) wires on Cu substrates and silicon (Si) chips, respectively, were developed. To overcome Cu oxidation issue, the bonding surface on the wire was plated a silver (Ag) layer. An annealing step followed to make the Ag layer much easier to deform and conform to the Cu or Si bonding surfaces. The bonding process was performed at 300 °C with 6.89 MPa. Wire-bond cross sections were studied using optical and electron microscopy, respectively. The images obtained exhibit nearly perfect Ag–Cu bonding interface. For wire-bonds made on Cu substrate, in-plane (shear) pull test measured a breaking of force 20.7–23.7 kg, comparable to the 22.5 kg breaking force of the Cu wire itself. Breaking forces on vertical (peel) pull test are about one-half of in-plane pull test results. For wire-bonds made on Si chip, breaking forces are about 80 % of those made on Cu substrate. Fracture modes were evaluated in details. 90 % of the wire-bonds broke with three modes mixed together: near Cu–Ag plating interface, inside Ag layer, and Ag–Cu bonding interface. Thus, the bonding interface is as strong as other regions of the wire-bond. This solid-state wire bonding process is expected to have valuable applications in high power and high temperature devices and modules where the wire-bonds have to stand alone without protection due to lack of high temperature molding compound and reinforcing materials.

Soldering is a process that joins two metal parts with a low-melting-point metal or alloy, called solder. It is widely recognized that intermetallic compound (IMC) formation is essential for the solder to bond to metals. The IMC layer grows during soldering. It grows further during usage, in particular, at temperature near the solder melting temperature. Extensive IMC growth can result in reliability issues. A reason is that IMC is much less ductile than the solder and does not deform as much as the solder to manage the coefficient of thermal expansion mismatch between the parts joined. In this paper, we looked into and developed a soldering process to fabricate IMC-less solder joints. The fundamental concept is to choose a barrier metal that can bond to solder without forming IMC with the solder. With our experience and Cr-Sn phase diagram, Cr is selected as the barrier metal. Several bonding experiments have been performed and the preliminary results show that high quality Sn joints could be produced with a little IMC formation before high-temperature aging. After aging at homologous temperature of 0.9 of Sn for 100-200 h, {\rm Cu}-{6}{\rm Sn} 5 and {\rm Cu}3 Sn IMCs are observed. They are caused by the penetration of molten Sn through microcracks or pinholes on the Cr layer to react with the underlying Cu. In production environment, the density of microcracks and pinholes can be greatly reduced to inhibit IMC growth, making the realization of solder joints without IMC a possibility. © 2011-2012 IEEE.

Two copper (Cu) substrates were bonded using silver (Ag) and indium (In) and annealed at 200-250 °C to convert the joints into the solid solution (Ag) for enhanced strength and ductility. Cu-Cu pair was chosen so that the samples break in the joint during shear test. The upper Cu was electroplated with 15 μm Ag. The lower Cu was plated with 15 μm Ag, followed by In and 0.1 μm Ag to inhibit indium oxidation. Two designs were implemented, using 8 μm and 5 μm In, respectively. The Cu substrates were bonded at 180 °C in 100 mTorr vacuum without flux. Afterwards, samples were annealed at 200 °C for 1000 h (first design) and at 250 °C for 350 h (second design), respectively. Scanning electron microscope with energy dispersive X-ray analysis (SEM and EDX) results indicate that the joint of the first design is an alloy of mostly (Ag) with micron-size Ag2In and (ζ) regions, and that of second design has converted to a single (Ag) phase. Shear test results show that the samples are very strong. The breaking forces far exceed requirements in MILSTD- 883H standards. Fracture incurs inside the joint and is a mix of brittle and ductile modes or only ductile mode. The joint solidus temperatures are 600 °C and 900 °C for the first and second designs, respectively. Copyright © 2014 by ASME.

In this paper, aluminum circuit boards (ACBs) were designed, fabricated, and tested to demonstrate the possibility and advantages of the ACB technology. Processes were developed to grow high quality alumina (Al2O3) on Al boards and coat thick copper (Cu) layer over the alumina to produce an Al/alumina/Cu structure. The measured resistance and breakdown voltage of the as-formed 50 um alumina layer is > 40 M and 600 VDC respectively. In this design, heat generated by a high power circuit component attached to the Cu layer can conduct through the alumina layer and reach the Al base. Alumina has much higher thermal conductivity than epoxy-glass insulating layer of the popular FR-4 printed circuit boards. The quality of the boards produced in this paper was evaluated rigorously using scanning electron microscope. To test the reliability of the boards, they were put through 500 cycles of thermal cycling test between -40 °C to 85 °C and 100 h of high temperature storage test at 250 °C. To ensure its compatibility with soldering operations, 10 mm × 12 mm Cu substrates were bonded to the Al boards using a fluxless tin process. The thickness of the joint is 9.4 um including the intermetallic layers. Despite significant coefficient of thermal expansion mismatch of the structure and large Cu size, the bonded samples show no sign of cracks, breakage, or degradation. © 2011-2012 IEEE.

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro-scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)5Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.

The reaction of indium (In) and silver (Ag) during the electroplating process of indium over a thick silver layer was investigated. It was found that the plated In atoms react with Ag to form AgIn2 intermetallic compounds at room temperature. Indium is commonly used in the electronics industry to bond delicate devices due to its low yield strength and low melting temperature. In this study, copper (Cu) substrates were electroplated with a 60-μm-thick Ag layer, followed by electroplating an In layer with a thickness of 5 μm or 10 μm, at room temperature. To investigate the chemical reaction between In and Ag, the microstructure and composition on the surface and the cross section of samples were observed by scanning electron microscopy (SEM) with energy-dispersive x-ray spectroscopy (EDX). The x-ray diffraction method (XRD) was also employed for phase identification. It was clear that indium atoms reacted with underlying Ag to form AgIn2 during the plating process. After the sample was stored at room temperature in air for 1 day, AgIn2 grew to 5 μm in thickness. With longer storage time, AgIn2 continued to grow until all indium atoms were consumed. The indium layer, thus, disappeared and could barely be detected by XRD.

Silver flip-chip joints between silicon (Si) chips and copper (Cu) substrates were fabricated using a solid-state bonding process without any solder and without flux. The bonding process was performed at 250[degrees]C, compatible with typical reflow temperature for lead-free solders. During the bonding process, there was no molten phase involved. The Ag joints fabricated consisted of only pure Ag without any intermetallic compound (IMC). Thus, reliability issues associated with IMCs and IMC growth do not exist anymore. Silver has the highest electrical conductivity and highest thermal conductivity among all metals. It is also quite ductile and able to deform to release stresses caused by thermal expansion mismatch. Flip-chip joints of high aspect ratio can be accomplished because the joints stay in a solid state during the bonding process. It looks like that silver is the ultimate joining material for fip-chip as well as through-Si-via interconnect technologies. In this study, the solid-state bonding process was first developed using a pure Ag foil to bond a Si chip to a Cu substrate in one step. The bonding strength on two interfaces, Si/Ag and Ag/Cu, passes the MIL-STD-883G Method 2019.7. To demonstrate Ag flip-chip interconnects, Si chips were electroplated with Ag bumps, followed by the solid-state bonding process on Cu substrates. The flip-chip bumps are well bonded to the Cu substrate. It would take some time for this new technology to be probably accepted and utilized in production. On the other hand, the preliminary results in this study show that Ag flip-chip joints can indeed be fabricated at 250[degrees]C. [DOI: 10.1115/1.4002297] Keywords: silver joints, flip-chip, direct bonding, solid-state bonding process, electronic packaging, integrated circuits

This article extends the findings from the Resources for Enhancing Alzheimer's Caregiver Health (REACH II) program, a multisite randomized clinical trial of a multicomponent psychosocial intervention, to improve the well-being of informal caregivers (CGs) of persons with dementia. We used residual change scores and stepwise hierarchical regression analyses to explore separately in 3 racial ethnic groups (Hispanic or Latino, Black or African American, and White or Caucasian) how the effects of the intervention were moderated by CG characteristics (sex, age, education, and relationship), CG resources (social support), and religious coping. The results indicated that CG's age and religious coping moderated the effects of the intervention for Hispanics and Blacks. The older Hispanic and Black CGs who received the intervention reported a decrease in CG burden from baseline to follow-up. Black CGs with less religious coping who received the intervention also reported a decrease in depressive symptoms from baseline to follow-up. Key Words: Caregiving--Psychotherapy--Social support--Well-being. doi: 10.1093/geronb/gbp131

A novel process of bonding silver (Ag) foils to copper (Cu) substrates has been developed. This direct bonding method does not use any intermediate layer in between. An important application of this process is electronic packaging where semiconductor device chips are bonded to Cu substrates or Cu electrodes fabricated on substrates. Cu is chosen as the major material for substrates and electrodes due to its high electrical and thermal conductivities, high strength, adequate rigidity, easiness in forging and machining, and low cost. On the other hand, Cu has a large mismatch in the coefficient of thermal expansion with most semiconductors, particularly with silicon. This makes it very difficult to bond large device chips to Cu substrates with a metallic joint. We thus design the Ag-cladded Cu structure to overcome this difficulty. Ag is quite soft and ductile. It can function as a strain buffer between the semiconductor chip and the Cu substrate. Ag also has superior physical properties. It has the highest electrical and thermal conductivities among all metals. In the beginning, we used an electroplating process to produce Ag-cladded Cu substrates. However, it is time consuming and costly to electroplate thick Ag layers. To obtain thick Ag layers (more than 200 [mu]m), this new laminating process is developed. The Ag foil is laminated to the Cu substrate directly with a static load of 1000 psi at 250[degrees]C in a 50 mtorr vacuum to suppress oxidation. No bonding medium is used. Scanning electron microscopy images on cross sections of bonded samples exhibit a perfect Ag-Cu bond. [DOI: 10.1115/1.2993144] Keywords: bonding, direct bonding, laminating, silver foil, copper substrate

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and groupnd electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3 dB for frequencies of up to 35 GHz and the return loss is higher than 15 dB for frequencies of up to 29 GHz using CPS flip-chip configuration. [DOI: 10.1115/1.2993140] Keywords: coplanar trasmission lines, coplanar waveguied, coplanar strip lines, flip-chip devices, packaging