196 results on '"Lee, Chiou-Yng"'
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2. Implementation of an FPGA-Based Vision Localization
3. Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm
4. Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination
5. Low-Space Complexity Finite Field Multiplier Using Both Dickson and Polynomial Bases
6. Pipeline Design of Bit-Parallel Gaussian Normal Basis Multiplier over GF(2m)
7. Hybrid Digit-Serial Multiplier for Shifted Polynomial Basis of GF(2 m )
8. Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber
9. Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor
10. CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy
11. Supporting Physical Agents in an Interactive e-book
12. Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm
13. Subquadratic Space-Complexity Parallel Systolic Multiplier Based on Karatsuba Algorithm and Block Recombination
14. Implementation of an FPGA-Based Vision Localization
15. Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2 m)
16. Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation
17. Low-complexity bit-parallel systolic multipliers over GF(2 m)
18. Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme
19. Efficient bit-parallel multipliers over finite fields GF(2.sup.m )
20. Low-complexity multiplexer-based normal basis multiplier over GF(2 m )
21. New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2m) Under Polynomial Basis and Normal Basis Representations
22. Multiplexer-based bit-parallel systolic multipliers over GF([2.sup.m])
23. Unified Parallel Systolic Multiplier Over ${\it GF}(2^{m})$
24. Low-Complexity Bit-Parallel Multiplier over GF(2m) Using Dual Basis Representation
25. Scalable and Systolic Architecture for Computing Double Exponentiation Over GF(2 m )
26. Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2 m )
27. Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 m )
28. Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
29. Scalable and Systolic Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector Representation
30. Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally spaced polynomials
31. Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2m) based on Bivariate Polynomial Basis Representation
32. Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy
33. Multiplexer-based double-exponentiation for normal basis of GF(2.sup.m )
34. Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis
35. Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach
36. LSM
37. High Capability and Low-Complexity: Novel Fault Detection Scheme for Finite Field Multipliers over GF(2m) based on MSPB
38. Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method
39. Embracing Systolic
40. Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm
41. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm
42. Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials
43. Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over$\textit{GF}(2^{m})$
44. High‐throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems
45. Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field
46. An efficient FPGA-based accelerator design for convolution
47. Low‐latency digit‐serial dual basis multiplier for lightweight cryptosystems
48. Hardware implementation of double basis multiplier using TMVP approach over GF (2m)
49. Decomposition of symmetric matrix–vector product over GF (2 m )
50. Gaussian normal basis multiplier over GF(2m) using hybrid subquadratic‐and‐quadratic TMVP approach for elliptic curve cryptography
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