550 results on '"Lee-Sup Kim"'
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2. ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks.
3. OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing.
4. Energy-Efficient CNN Personalized Training by Adaptive Data Reformation.
5. Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor.
6. Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators.
7. MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT.
8. Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators.
9. Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN.
10. Quantization-Error-Robust Deep Neural Network for Embedded Accelerators.
11. A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture.
12. Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks.
13. S-FLASH: A NAND Flash-Based Deep Neural Network Accelerator Exploiting Bit-Level Sparsity.
14. A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type.
15. EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access.
16. A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation.
17. Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity.
18. A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators.
19. Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices.
20. Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator.
21. A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration.
22. A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates.
23. Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks.
24. A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices.
25. Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration.
26. An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM.
27. eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators.
28. A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks.
29. NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks.
30. CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator.
31. A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE With Non-Time-Overlapping Data Generation for 4: 1 CMOS Clockless Multiplexer.
32. An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices.
33. An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS.
34. TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training.
35. A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS.
36. A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control.
37. Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory.
38. DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells.
39. SENIN: An energy-efficient sparse neuromorphic system with on-chip learning.
40. Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph Cut in Resistor Grid.
41. A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks.
42. A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method.
43. A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE.
44. Elaborate Refresh: A Fine Granularity Retention Management for Deep Submicron DRAMs.
45. Crosstalk avoidance code for direct pass-through architecture.
46. Energy Efficient Data Encoding in DRAM Channels Exploiting Data Value Similarity.
47. An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface.
48. Energy-Efficient Design of Processing Element for Convolutional Neural Network.
49. A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network.
50. In-DRAM Data Initialization.
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