46 results on '"Lei, Yuanwu"'
Search Results
2. Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions
3. Platform-Adaptive High-Throughput Surveillance Video Condensation on Heterogeneous Processor Clusters
4. Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithm
5. Accelerating Molecular Dynamics Simulations on Heterogeneous Architecture
6. Designing Parallel Sparse Matrix Transposition Algorithm Using ELLPACK-R for GPUs
7. Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs
8. FPGA Implementation of Variable-Precision Floating-Point Arithmetic
9. A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA
10. Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
11. FPGA implementation of an exact dot product and its application in variable-precision floating-point arithmetic
12. Pipelined Range Reduction Based Truncated Multiplier
13. Comparative Analysis of FPGA-Based Pair-HMM Accelerator Structures
14. Efficient Large-Scale 1D FFT Vectorization on Multi-Core Vector Accelerator
15. An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators
16. MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing
17. Pair-HMM accelerator based on non-cooperative structure
18. A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
19. Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm
20. High‐Performance FP Divider with Sharing Multipliers Based on Goldschmidt Algorithm
21. Low‐Latency SRT Division and Square Root Based on Remainder and Quotient Prediction
22. Configurable Floating‐Point FFT Accelerator on FPGA Based Multiple‐Rotation CORDIC
23. Multi-bit transient fault control for NoC links using 2D fault coding method
24. PR-ELM: Parallel regularized extreme learning machine based on cluster
25. Classification of Hyperspectral Remote Sensing Image Using Hierarchical Local-Receptive-Field-Based Extreme Learning Machine
26. An efficient and effective convolutional auto-encoder extreme learning machine network for 3d feature learning
27. Area-efficient high-throughput sorted QR decomposition-based MIMO detector on FPGA
28. An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm
29. A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme
30. Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
31. FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function
32. Design of Double-Precision Floating-Point Division and Square Root Based on SRT Algorithm
33. Transpose-free variable-size FFT accelerator based on-chip SRAM
34. VLIW coprocessor for IEEE-754 quadruple-precision elementary functions
35. CPU-GPU hybrid parallel strategy for cosmological simulations
36. Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access
37. Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
38. Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA
39. VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic
40. FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic
41. FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing
42. A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs
43. Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
44. Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA
45. FPGA SAR Processor with Window Memory Accesses
46. CPU-GPU hybrid parallel strategy for cosmological simulations.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.