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2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch ION/IOFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions. [ABSTRACT FROM AUTHOR]

Self-aligned double (SADP) or quadruple (SAQP) patternings have been used to obtain sub-resolution lithographies (sub-10 nm). For this purpose, usually, these patternings are integrated with 193 nm immersion (193iL), extreme ultra-violet (EUVL) and electron beam (EBL) lithographies. In this work, SADPs are integrated with Ga+ Focused Ion Beam (FIB) milling, which is a novel alternative to traditional 193iL, EUVL and EBL, mainly for prototyping of nanodevices. Furthermore, the FIB milling is a maskless process, thus being more flexible than EBL and cheaper than EUVL. The FIB milling was carried out on the a-Si:H/Al (deposited on Si substrate) to pattern the parallel Al nanowires (AlNWs), which are used as mandrel in our SADP. The a-Si:H layer, used as spacer in our SADP, also is an effective barrier against the Ga+ ion bombardment directly on Al surface, avoiding damages on the AlNW mandrel. Thus, after FIB milling, SADP and plasma etch steps, Silicon Nano-Wires (SiNWs), with dimensions (extracted by Scaning Electron Microscopy (SEM)) of fin width and pitch of 35 nm and 170 nm, respectively, were obtained. This is an excellent result, similar to obtained by SADP methods integrated with traditional lithographies. Therefore, our SADP with FIB milling is a flexible alternative to obtain SiNWs for 3D nanostructure technologies prototypes. Furthermore, a last important result, extracted from energy dispersive x-ray spectroscopy (EDS) spectrum, is the Ga peak absence, indicating that no trace of gallium (for an EDS detection limit of 1%) could be detected into SiNWs. This result agrees the TRIM (Transport and Range of Ions in Matter) simulation of gallium ion implantation in a-Si:H/Al structure. Unlabelled Image • Hydrogenated amorphous silicon layer were used as spacers in a novel Self-Aligned Double patterning. • Aluminum film was used as mandrel in a novel Self-Aligned Double patterning. • Hydrogenated amorphous silicon layer were also used as barrier against gallium incorporation during Focused Ion Beam milling. • Silicon nanowires were obtained with dimensions smaller than 50 nm and the pitch in the order of hundreds of nanometers. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]