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This paper presents a new methodology of analyzing phase noise in a ring oscillator by time-scaling the thermal noise. Close-form solutions that relate the probability distribution and power-spectral density of the phase noise to circuit parameters have been obtained. These close-form solutions characterize the behavior of phase noise even when the circuit is varying with time in a nonlinear fashion. Specifically, the theory predicts that for a given oscillation frequency, phase noise roughly decreases as the cube of the delay cell charging current value at threshold crossing; thus, it provides new design insights. Simulations were run and verified this dependency. Index Terms--Frequency synthesizer, jitter, phase-locked loop (PLL), phase noise, relaxation oscillator, ring oscillator.

Ring oscillators' phase noise, when their delay cells are modeled as buffers and the noise sources assumed to be thermal noise, has some distinctive characteristics. We investigate one of the distinct characteristics, the threshold crossing property. The resulting model is shown to arise from the last passage time behavior of thermal noise present in the circuits. Simulation results on ring oscillators operating in gigahertz range and having timing jitter in picoseconds range confirm the model. Index Terms--Jitter, phase noise, ring oscillator.

We analyze three different sources of noise in a sampling mixer working at radio frequency (RF) or intermediate frequency. External RF and intrinsic noise are analyzed using conventional frequency domain methods. External local oscillator (LO) noise is analyzed in time domain by solving a stochastic differential equation. We are able to take into account the time-varying aspect of the LO noise coupling, and show that LO noise becomes important at high frequencies. Analytical expression for LO noise is obtained, which can be used to guide mixer design. LO noise is in additional to LO jitter, which should be combined with noise analysis to give a complete picture. Index Terms - Intermediate frequency (IF), noise, radio frequency (RF), sampling mixer, stochastic differential equation (SDE).

A new method for the stabilization of high-order (> 2) single-stage single-bit oversampling A/D converters is proposed. In this approach, the stability of the modulator is achieved by preventing any unbounded increase in the internal node-voltages through the insertion of local feedback signals inside the modulator loop. In the past, absolute bounds for stability have been derived for the first-order converter. This property is exploited in stabilizing a higher order loop by activating local first-order loops as soon as the internal integrators overload. With local feedback, individual integrators are prevented from saturating and the output voltages are within the proper bounds. The error caused by the local feedback signals is cancelled by feeding these signals through alternate signal paths, in a way similar to the quantization noise cancellation mechanism in a MASH architecture. Since the frequency of overloading can be made very low by proper design, the effect of imperfect cancellation due to mismatches in the two signal paths caused by the modulator nonidealities is quite small. Hence, compared to the inherently stable MASH architectures, the proposed approach achieves stability and is yet much less sensitive to component mismatches. In a sampled data environment where the integrator is realized using opamps, this translates into a low opamp gain requirement. Simulation results confirm that third order modulators using opamps with gain as low as 50 achieve a peak signal-to-noise ratio (SNR) of about 83 dB with an oversampling ratio of 64. This is less than 1 dB from the SNR achieved with infinite opamp gain. In this modern day of low voltage CMOS design, such a low opamp gain can be easily realized since no cascode stage is required.

A novel approach for CMOS pipelined analog-to-digital conversion based on switched-capacitor implementation is proposed. This converter's differential nonlinearity (DNL) is independent of any element mismatches in residue amplification. Derivations of the causes on DNL errors in conventional architectures are presented. The DNL of any pipelined converter is dependent upon the conditioning of the residue in the sub-digital-to-analog converter (sub-DAC) and interstage gain stages more than in the choice threshold of the sub-analog-to-digital converter. With well-conditioned residue, any errors made in the sub-DAC's of any earlier stage are evenly distributed over the range of subsequent stages' digital codes. This property is exploited in the design of the proposed converter, which achieves a measured 12-bit resolution and a simulated resolution of 13 bits, even under a 5% mismatch in capacitor ratios. The prototype is implemented using an operational transconductance amplifier with gain boosting. The ADC runs at 10 MHz (3.3 Ms/s). Index Terms - Capacitor mismatch, differential nonlinearity (DNL), digital error correction, gain boosting, integral nonlinearity (INL), operational transconductance amplifier (OTA), pipelined analog-to-digital converter.

A time-varying theory of Volterra series is developed and applied in the sampled-data domain to solve for harmonic and intermodulation distortion of a MOS-based track-and-hold sampling mixer with a nonzero fall-time LO waveform. Distortion due to sampling error is also calculated. These results, when combined with the continuous-time solution, quantify harmonic and intermodulation distortion of a track-and-hold type mixer completely. Closed-form solutions are obtained. As a practical consequence, it is shown that for certain fall-time, the distortion of track-and-hold mixers can be better than what would be predicted by a simple application of time-invariant Volterra series theory. Index Terms - Harmonic distortion, intermodulation distortion, intermediate frequency (IF), radio frequency (RF), time-varying Volterra series, track-and-hold sampling mixer.

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the secondstage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new Iow-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-µm CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of --55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm°. [ABSTRACT FROM AUTHOR]