96 results on '"Li, James Chien-Mo"'
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2. Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis
3. High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
4. Small Sampling Overhead Error Mitigation for Quantum Circuits
5. Small Sampling Overhead Error Mitigation for Quantum Circuits
6. Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips
7. ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption
8. Diagnosing Double Faulty Chains through Failing Bit Separation
9. Machine Learning-Based Test Pattern Generation for Neuromorphic Chips
10. Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
11. Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
12. Fault Modeling and Testing of Spiking Neural Network Chips
13. An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
14. qATG: Automatic Test Generation for Quantum Circuits
15. Diagnosis technique for Clustered Multiple Transition Delay Faults
16. High Efficiency and Low Overkill Testing for Probabilistic Circuits
17. ATPG and Test Compression for Probabilistic Circuits
18. DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG
19. Test methodology for PCHB/PCFB Asynchronous Circuits
20. Parallel order ATPG for test compaction
21. Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations
22. Test Pattern Compression for Probabilistic Circuits
23. Physical-aware diagnosis of multiple interconnect defects
24. Robust test pattern generation for hold-time faults in nanometer technologies
25. PSN‐aware circuit test timing prediction using machine learning
26. Automatic Test Pattern Generation
27. A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse
28. Test Pattern Modification for Average IR-Drop Reduction
29. Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration
30. Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
31. TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects
32. A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects
33. Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk
34. GPU-based timing-aware test generation for small delay defects
35. Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits
36. Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects
37. Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics
38. Test Generation of Path Delay Faults Induced by Defects in Power TSV
39. GPU-based n-detect transition fault ATPG
40. Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
41. Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
42. An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example
43. Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis
44. A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
45. Placement Optimization of Flexible TFT Digital Circuits
46. Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
47. Reliability Screening of a-Si TFT Circuits: Very-Low Voltage and ${\rm I}_{\rm DDQ}$ Testing
48. Static timing analysis for flexible TFT circuits
49. CSER: BISER-based concurrent soft-error resilience
50. DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In
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