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This paper presents two endfire on-chip antennas (OCAs) at 140 and 320 GHz using a standard 0.13- $\mu \text{m}$ SiGeBiCMOS technology; quasi-Yagi antenna concept is used with loaded dielectric. In order to eliminate the influence of the low-resistivity silicon substrate, the substrate thickness is chosen as $\sim 84~\mu \text{m}$ (for 140 GHz), and the antenna is mounted on the edge of a metal supporter with the front part ungrounded. The loaded dielectric is designed using the silicon and silicon dioxide (SiO2) layers to improve the gain. The antenna shows the measured impedance bandwidth of >45% at 140 GHz, with the peak gain of 4.1 dBi, and the simulated peak radiation efficiency of 83%. A $1 \times 2$ array at 140 GHz is also designed and implemented; the corresponding measured impedance bandwidth, peak gain, and simulated radiation efficiency are >36%, 7 dBi, and 72%, respectively. With the proposed structure, the OCA at 320 GHz is also designed and fabricated with the substrate thickness of $\sim 34~\mu \text{m}$ . The measured gain of 3.9 dBi and the simulated radiation efficiency of 80% are achieved at 320 GHz, respectively.

This paper presents the detailed design and demonstration of a Ka-band single-chip transmit (TX)/receive (RX) front-end in 0.13- $\mu \text{m}$ SiGe BiCMOS technology. The front-end includes single-pole double-throw (SPDT) switches, low-noise amplifier, loss compensation amplifiers (LCAs), phase shifter, and power amplifier. Distributed structures are utilized in gain amplifiers to ensure broadband performance while stacked structure is adopted in power amplifier to deliver high output power in the TX mode. A 5-b phase shifter with design strategies for low rms phase/gain errors serves as the common leg of the RX and TX paths. In the RX mode, measurements show a gain of 17 dB, an output $P_{\mathrm { {-1~dB}}}$ of −1 dBm, an rms phase error less than 4°, and an rms gain error less than 0.6 dB with 0.528-W dc power from 30 to 40 GHz. In the TX mode, measurements show a gain of 14 dB, an output $P_{\mathrm { {-1~dB}}}$ of 20.5 dBm, an rms phase error less than 3.7°, and an rms gain error less than 0.55 dB with 1.587-W dc power from 30 to 40 GHz. The whole front-end occupies $3.2 \times 2.2$ mm2 including the testing pads. By choosing inductors and capacitors with reasonable values, designing a well-matched SPDT switch with high isolation, and optimum ordering of phase shift cells and LCAs in the phase shifter design, this TX/RX front-end achieves excellent rms phase/gain error performance without any trimming in a system-level measurement at Ka-band.

This paper presents the design of an X-band phased-array transceiver core chip in 0.13- $\mu{\hbox{m}}$ SiGe BiCMOS technology. The system is based on the all-RF architecture and contains switches, low-noise amplifier (LNA), power amplifier (PA), and the common leg 5-bit phase shifter with loss compensation amplifiers. A distributed structure is used in the gain amplifiers design to ease the multi-stage gain roll-off in the transmit (TX)/receive (RX) paths. A distributed LNA is utilized in the RX path to achieve broadband amplification with acceptable noise figure (NF) while a stacked PA is utilized in the TX path to get high output power. In the RX mode, the receiver demonstrates a gain of $> {\hbox{25 dB}}$ , an average NF of 3 dB, an output ${ P} _{-1~{\rm dB}}$ of 6 dBm, a root mean square (rms) phase error less than 3.8 $^{\circ}$ and an rms gain error less than 1.2 dB from 9 to 11 GHz; while dissipating 352-mW dc power. In the TX mode, the transmitter demonstrates a gain of $> {\hbox{22 dB}}$ , an output ${ P} _{-1~{\rm dB}}$ of 28 dBm, an rms phase error less than 3 $^{\circ}$ , and an rms gain error less than 0.6 dB from 9 to 11 GHz; while dissipating 4.128-W dc power. The whole transceiver occupies 5.2 $\,\times\,$ 3 ${\hbox{mm}}^{2}$ chip area including the testing pads.

A 340-GHz on-chip antenna (OCA) with high-gain and high-radiation efficiency is designed using a standard ${0}.{13}\hbox{-}\upmu {\rm m}$ SiGe BiCMOS technology without any postprocesses. In the proposed OCA structure, a rectangular slot loop is etched in the upper wall of a substrate integrated waveguide (SIW) to form a magnetic current loop radiator. The SIW structure forms a back cavity to suppress the surface waves and separate the radiation aperture from the low-resistivity substrate. Furthermore, the side wall of the SIW cavity and the edge of the slot form a ${{{\lambda }}_{{g}}}/4$ resonator to reflect the power back to the slot loop. As a result, the radiation efficiency is improved. By etching a slot properly in the SIW upper wall, another resonating point is constructed and hence, the bandwidth is broadened. Single antenna element and a ${2} \times {2}$ array are both designed and fabricated with- and without- the slot structure; a maximum gain of 7.9 dBi with the radiation efficiency of 48% at 340 GHz is achieved for the proposed SIW cavity-backed antenna structure.

This paper presents the design of terahertz 2× and 4× sub-harmonic down-mixers using Schottky Barrier Diodes fabricated in standard 0.13 μm SiGe BiCMOS technology. The 340 GHz sub-harmonic mixers (SHMs) are designed based on anti-parallel-diode-pairs (APDPs). With the 2nd and 4th harmonic, local oscillator (LO) frequencies of 170 GHz and 85 GHz are used to pump the two 340 GHz SHMs. With LO power of 7 dBm, the 2× SHM exhibits a conversion loss of 34.5–37 dB in the lower band (320–340 GHz) and 35.5–41 dB in the upper band (340–360 GHz), with LO power of 9 dBm, the 4× SHM exhibits a conversion loss of 39–43 dB in the lower band (320–340 GHz) and 40–48 dB in the upper band (340–360 GHz). The measured input 1-dB conversion gain compression point for the 2× and 4× SHMs are −8 dBm and −10 dBm at 325 GHz, respectively. The simulated LO-IF (intermediate frequency) isolation of the 2× SHM is 21.5 dB, and the measured LO-IF isolation of the 4× SHM is 32 dB. The chip areas of the 2× and 4× SHMs are 330 μm × 580 μm and 550 μm × 610 μm, respectively, including the testing pads.

A 4×4 power amplifier (PA) array with end-fire on chip antennas is presented in this paper. In the PA array module, four-chips are stacked vertically and spaced by the metal holders. In a single chip, four PA blocks with a 1×4 end-fire on-chip antenna are integrated. 0.13-µm SiGe BiCMOS process is used for fabrication with the experimental ƒ T and ƒ MAX of 210 and 260 GHz, respectively. The 4×4-PA-array module achieves a measured maximal effective isotropic radiated power (EIRP) of 39 dBm at 135GHz. The whole module has the physical dimensions of 24×35×24 mm3 and it consumes 19 W from a 6.5 V DC supply. This module can easily be scaled to any M×N array and hence, further improve the EIRP.

A method to enhance transition performance between millimeter wave & terahertz Si-based chip and waveguide by employing improved waveguide probe coupling structure is proposed in this paper. Multi-section impedance matching structure is employed in the E-plane probe to obtain good matching/low loss performance for waveguide packaging. In order to eliminate severely higher order dielectric filled waveguide mode excited below the metal layer one in the lossy silicon substrate, a simple but effective shielding method is proposed to prevent the higher order mode loss, which can decrease the signal energy injecting into lossy substrate to improve the insertion loss performance considerably. Finally, an W-band Si-based amplifier is demonstrated, and measured results show that good agreements between the measured and simulated results are achieved.

This paper presents a W-band zero intermediate frequency (Zero-IF) fundamental down conversion mixer in 0.13 pm SiGe BiCMOS technology. Single balanced Gilbert cell is utilized as a core of mixer. RF signal is fed through an on-chip Lange coupler to realize I-Q channels. Measured results show that the conversion gain is greater than 7.5 dB from 83.5 GHz to 86 GHz when LO is fixed at 85 GHz with power lever of −3 dBm; and if IF is fixed at 300 MHz, the conversion gain is above 9.5 dB from 83 GHz to 86 GHz with LO@-3 dBm pumped, the I-Q channels are with differential IF outputs to facilitate differential-input baseband applications. The RF return loss is better than 20 dB over 70-to-100 GHz, and LO port return loss is better than 10 dB from 80 GHz to 90 GHz. The LO to RF isolation is more than 35 dB from 70 GHz to 110 GHz. The mixer consumes 57 mW DC power with 0.8×0.8 mm2 chip size.